In short: The salicide (self-aligned silicide) process reacts a refractory metal such as cobalt or nickel with exposed silicon on the gate, source and drain to form a low-resistance silicide only where the metal touches silicon, slashing contact and sheet resistance without any extra mask.
Every transistor you design in a modern SoC has a dirty secret: the silicon itself is a mediocre conductor. Doped polysilicon gates and silicon source/drain regions carry a sheet resistance of roughly 50–200 ohms per square, and the metal-to-silicon contact resistivity can be enormous. On a 1 GHz design, that parasitic resistance turns into RC delay that eats your timing budget alive. The salicide process is the elegant, decades-old answer, and understanding it is a staple of any physical-design or process-integration interview.
What "salicide" actually means
The word is a contraction of self-aligned silicide. A silicide is a compound of a metal and silicon (CoSi₂, NiSi, TiSi₂). "Self-aligned" is the clever part: the silicide forms only where the deposited metal sits directly on bare silicon. Over the gate oxide spacers and field oxide, the metal has nothing to react with, so after an etch it is simply washed away, leaving silicide precisely registered to the active regions. No lithography step defines it, so there is zero overlay error and zero added mask cost.
Typical numbers: unsilicided n+ source/drain sheet resistance ≈ 80–120 Ω/□. After CoSi₂ salicidation it drops to ≈ 4–8 Ω/□ — a 15–20× improvement. NiSi gets you to ≈ 3–6 Ω/□ with far less silicon consumption.
Why we moved from TiSi₂ to CoSi₂ to NiSi
Early CMOS (0.5–0.35 µm) used titanium silicide. TiSi₂ suffers the infamous "narrow-line effect": the low-resistance C54 phase will not nucleate on sub-0.2 µm lines, so resistance shot up exactly where geometries shrank. Cobalt (0.25–0.09 µm) solved that — CoSi₂ is insensitive to line width — but cobalt consumes a lot of silicon (≈ 3.6 nm Si per nm Co), which is fatal for ultra-shallow junctions. From 65 nm onward, nickel took over: NiSi forms at low temperature (~400–500 °C), consumes little silicon, and has low resistivity. The trade-off is that NiSi is thermally fragile and degrades to high-resistance NiSi₂ if you overheat it.
The formation steps, in order
The flow is a textbook example of a self-limiting, self-aligning integration scheme:
- Surface prep. A dilute-HF dip removes native oxide — critical, because even 1 nm of SiO₂ blocks the silicide reaction and causes voids.
- Metal deposition. A thin (10–20 nm) blanket layer of Ni or Co is sputtered over the whole wafer, usually capped with TiN to prevent oxidation during anneal.
- First RTA (RTA1). A rapid thermal anneal forms a high-resistance, metal-rich phase (e.g. Ni₂Si, or CoSi) only where metal meets silicon. Spacers and STI see no reaction.
- Selective etch. A wet strip (e.g. a piranha / SPM clean) removes unreacted metal and the TiN cap from the dielectric. This is the self-aligning moment.
- Second RTA (RTA2). A higher-temperature anneal transforms the metal-rich phase into the final low-resistance phase (CoSi₂ or NiSi).
The self-aligning mechanism, watched in motion
The animation below shows the key idea: a blanket metal layer anneals, reacts only over silicon, and the leftover metal on the dielectric is stripped — leaving silicide exactly where it belongs.
Silicide comparison at a glance
| Property | TiSi₂ (C54) | CoSi₂ | NiSi |
|---|---|---|---|
| Node era | 0.5–0.35 µm | 0.25–90 nm | 65 nm and below |
| Resistivity (µΩ·cm) | 13–16 | 15–20 | 10–18 |
| Formation temp | ~800 °C | ~700 °C | ~450 °C |
| Si consumed | moderate | high (~3.6 nm/nm) | low (~1.8 nm/nm) |
| Main weakness | narrow-line effect | Si consumption | thermal instability → NiSi₂ |
Where salicide fails — and how designers see it
Three defects dominate yield discussions. Bridging occurs when silicide creeps over the spacer and shorts gate to source/drain; it shows up as a leaky transistor. Piping / spiking happens when silicide punches through a shallow junction, causing junction leakage. And agglomeration is the thermal breakup of NiSi into high-resistance islands after a later thermal step. Process integrators use a silicide block (SAB / RPO) mask to deliberately keep silicide off certain regions — precision resistors, ESD ballast resistors, and I/O devices all rely on this.
Interview nugget: if a layout engineer asks for a high-value poly resistor, they place it under a silicide-block layer. Without it, the silicide shorts out the resistance and the resistor is useless.
In the design flow, the silicide layer is captured in the technology LEF/tech file and the extracted RC netlist. Tools such as Synopsys StarRC and Cadence Quantus read the silicide sheet-resistance values from the ITF/QRC tech file during parasitic extraction, which is why a wrong silicide model silently corrupts your timing signoff in PrimeTime or Tempus.
Where it fits with contacts and interconnect
Salicide is the bottom rung of the resistance ladder. Above it sit the tungsten contacts landing on the silicide, and above those the copper interconnect formed by the damascene copper process. If you want the full back-end picture, pair this article with our note on shallow trench isolation, since STI is what the self-aligned etch relies on to separate active regions. Teams building real tape-out flows often lean on hands-on VLSI design and physical-verification services to validate these process assumptions against silicon.
Want to go from "I've heard of salicide" to explaining RTA1/RTA2 phase transitions in an interview? Our CourseTron Nano Fab track walks the full front-end-of-line flow with real cross-sections and TCAD examples.
Frequently asked questions
Why is it called "self-aligned"?
Because no mask defines the silicide. The metal reacts only on exposed silicon; everywhere else (spacers, STI) it stays metallic and is etched away. The silicide ends up perfectly registered to the active regions with zero overlay error.
Why two anneals instead of one?
The first RTA forms a high-resistance metal-rich phase at a temperature low enough to stay selective and avoid bridging. After the unreacted metal is stripped, the second, hotter RTA converts that phase into the final low-resistance silicide. Splitting the reaction keeps it controlled and defect-free.
Why did the industry switch from cobalt to nickel?
Shrinking junctions could no longer tolerate cobalt's heavy silicon consumption. NiSi forms at lower temperature, consumes roughly half the silicon, and keeps low resistivity — essential for ultra-shallow source/drain at 65 nm and below.
Can silicide be blocked on purpose?
Yes. A silicide-block (SAB/RPO) mask prevents silicide formation over poly resistors, ESD ballast resistors, and certain I/O devices where you need the native silicon resistance preserved.