In short: Photolithography is the optical patterning step that projects a mask's circuit geometry onto a photoresist-coated wafer, chemically defining where every transistor, wire and contact will later be etched or doped.
Every integrated circuit you use, from the microcontroller in a washing machine to a 3 nm mobile SoC, exists because a pattern was transferred from a quartz plate onto silicon with light. That transfer step is photolithography, and a modern logic wafer passes through it 50 to 90 times before it is finished. Understanding it is non-negotiable for anyone entering fabrication, process integration, or even physical design, because the lithographic "ground rules" dictate what layout a designer is allowed to draw.
What problem does photolithography actually solve?
A chip is a stack of patterned layers: active regions, polysilicon gates, several metal interconnect levels, vias, and so on. The fab needs a way to say "etch here, not there" or "implant dopant here, not there" with nanometre precision across a 300 mm wafer carrying hundreds of dies. Photolithography provides that selectivity by creating a temporary polymer stencil, the resist, that protects some areas and exposes others to the next process step (etch, implant, or deposition lift-off). It is the only step that defines geometry; everything else transfers or fills that geometry.
A single advanced EUV exposure tool (ASML's NXE/EXE series) can cost well over US$150 million and prints features using 13.5 nm wavelength light. Lithography and its metrology routinely account for 30–40% of total wafer-processing cost at leading nodes.
The core sequence, step by step
A lithography "loop" is a tightly ordered recipe. Miss the order and the layer is scrap.
- Substrate prep & priming: the wafer is dehydration-baked and coated with HMDS to make the surface hydrophobic so resist adheres.
- Spin coating: liquid photoresist is dispensed and spun at 1,500–4,000 rpm to form a uniform film, often 50–500 nm thick. Spin speed and viscosity set the thickness.
- Soft bake: ~90–110 °C to drive off solvent and stabilise the film.
- Alignment & exposure: a stepper/scanner aligns to previous-layer marks (overlay) and projects the mask (reticle) image through a reduction lens, typically 4×, onto the resist.
- Post-exposure bake (PEB): critical for chemically amplified resists; it drives the acid-catalysed reaction that changes solubility.
- Develop: a developer such as TMAH dissolves the soluble regions, leaving the stencil.
- Hard bake & inspect: the pattern is hardened and metrology (CD-SEM, scatterometry) checks line width and overlay before the wafer moves to etch or implant.
Positive vs. negative resist
The chemistry of the resist decides whether exposed regions stay or go. This single choice flips the polarity of your entire mask.
| Property | Positive resist | Negative resist |
|---|---|---|
| Exposed region | Becomes soluble, washes away | Cross-links, stays |
| Resolution | Historically better; dominant in CMOS | Good; swelling can distort fine lines |
| Typical use | Leading-edge logic/memory | Lift-off, thick films, some EUV chemistries |
Resolution: why wavelength rules everything
The smallest half-pitch a tool can print follows the Rayleigh criterion, CD = k₁ × λ / NA. Here λ is the exposure wavelength, NA is the numerical aperture of the projection lens, and k₁ is a process factor (physically limited near 0.25 for single exposure). To shrink features you push λ down, NA up, or k₁ down with resolution-enhancement techniques.
That equation explains the industry's wavelength history: 365 nm i-line, then 248 nm KrF, then 193 nm ArF, then 193 nm immersion (water raises effective NA past 1.0), and finally 13.5 nm EUV. When optics stalled at 193 nm immersion for years, fabs bridged the gap with multiple patterning (LELE, SADP, SAQP), splitting one dense layer across several masks and etch steps.
Going from 193 nm ArF immersion to 13.5 nm EUV is roughly a 14× wavelength reduction, which is what let foundries collapse multi-mask patterning back into single EUV exposures at the 7/5 nm nodes and reduce step count, cycle time and defect sources.
Masks, OPC and computational lithography
At these dimensions the printed shape no longer matches what the designer drew. Diffraction rounds corners and shortens line ends. Fabs compensate with Optical Proximity Correction (OPC) and Inverse Lithography Technology (ILT), which deliberately distort the mask (adding serifs, assist features, hammerheads) so the wafer prints the intended shape. This "computational lithography" is a major EDA domain: Synopsys (Proteus, S-Litho), Siemens EDA (Calibre OPC/nmOPC), and Cadence supply the tools that turn a verified layout into a manufacturable reticle. Design-rule checks and DFM decks tie the physical-design world directly to the litho process.
A worked example: the overlay budget
Suppose a via layer must land on a metal line 20 nm wide. If your overlay (layer-to-layer alignment error) 3σ is 4 nm and your CD variation adds another few nm, you can quickly consume the margin before a via misses its landing pad and opens the connection. This is why scanners obsess over sub-nanometre overlay and why metrology after develop is as important as the exposure itself.
Where photolithography sits in the full flow
Lithography never acts alone. It creates the stencil; the next unit process acts through it. The most common partner is etch, where the exposed silicon, oxide or metal is removed while the resist protects the rest. If you want the other half of the picture, read our companion piece on what etching is in semiconductor fabrication, and for the step that places dopants through the resist openings, see what ion implantation is. Together these form the pattern-transfer backbone of every CMOS process.
If you want hands-on, tool-driven training in physical design and DFM that respects these litho constraints, our partner Avecas VLSI design services works with the same industry flows we teach.
Ready to go deeper? CourseTron's Nano Fabrication track walks you from resist chemistry to EUV and computational lithography with real recipe examples. Explore the Nano Fab courses →
Frequently asked questions
Why is it called "lithography"?
The term borrows from the printing art of lithography ("stone writing"), where ink adheres only to patterned regions. In chips, light defines the pattern instead of grease and water, so the prefix "photo" is added.
What is the difference between a stepper and a scanner?
A stepper exposes one full reticle field, then physically steps the wafer to the next die and flashes again. A scanner synchronously moves the reticle and wafer stages while exposing a slit, enabling larger fields and better aberration control. Modern leading-edge tools are scanners.
Why did the industry move to EUV?
193 nm immersion ran out of resolution for dense layers, forcing expensive multiple-patterning. EUV's 13.5 nm wavelength restores single-exposure printing of fine features, cutting mask count and defect opportunities despite its own complexity (vacuum optics, reflective masks, tin-plasma source).
Does photolithography define every layer of a chip?
Yes, every patterned layer, active, poly, each metal and via, needs its own mask and litho step. A leading logic process can require 50–90 litho operations, which is why throughput and overlay are such dominant economic factors.