Courses
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Learn UCIe – the open standard for chiplet-based die-to-die interconnects. Covers UCIe physical and protocol layers, die-to-die adapter architecture, advanced and standard packaging form factors, and UCIe IP integration strategy.
0 Lessons
Hours
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Learn HBM3 – the ultra-high-bandwidth memory used in AI accelerators and GPUs. Covers HBM3 architecture, 3D stacking (TSV), wide 1024-bit interface, refresh management, thermal design, and HBM3 PHY interface. Essential for AI chips, GPUs, and network processors.
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Hours
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Master CXL – the emerging coherent interconnect for CPU-accelerator-memory systems. Covers CXL 1.1/2.0/3.0 specifications, CXL.io, CXL.cache, CXL.mem, and CXL switch topology. Essential for AI accelerator, HPC, and data centre SoC engineers.
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Hours
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Learn NVMe (NVM Express) – the high-performance storage protocol over PCIe. Covers NVMe command set, submission/completion queue pairs, admin commands, NVMe namespaces, power management, and NVMe-oF with NVMe controller DV methodology.
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Hours
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Learn the DisplayPort protocol for high-resolution display interfaces. Covers DP 1.4 and DP 2.0 (UHBR) architecture, main link and AUX channel, link training, MST, HDCP 2.3, DSC, and USB-C integration. Targeted at multimedia SoC and GPU design engineers.
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Hours
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Learn UART – the most fundamental serial communication protocol. Covers UART framing (start/stop/parity bits), baud rate generation, RS232/RS485 levels, FIFO-buffered UART design, flow control (RTS/CTS), and UART controller RTL implementation.
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Hours
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Master the I2C protocol for sensor and peripheral interfaces. Covers I2C multi-master arbitration, clock stretching, 10-bit addressing, SMBus extensions, I2C timing analysis, and I2C controller RTL implementation with bus contention and NAK scenario testing.
32 Lessons
16:05:01 Hours
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Learn the SPI protocol for embedded and SoC design. Covers SPI modes (CPOL/CPHA), master/slave architecture, full-duplex transfers, multi-slave topologies, Quad-SPI (QSPI) for NOR flash, and SPI controller RTL design with UVM SPI VIP verification.
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Hours
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Learn USB4 – the convergence of USB and Thunderbolt 3 at 40Gbps. Covers USB4 tunnelling architecture (USB 3.2, DisplayPort, PCIe tunnels), bandwidth management, USB4 hub topology, power delivery 3.0, and backwards compatibility.
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Hours