Learn the AMBA AXI3 protocol through published lessons on architecture, signals, handshaking, burst transactions, transfer attributes and interconnect behaviour. The course also covers RTL design in Verilog and a SystemVerilog verification environment with monitors, scoreboards, coverage, assertions and test cases.
One-time course purchase
₹10000 20% off
Base course price: ₹7999 INR
Converted prices are estimates. Confirm the final amount and currency on the payment screen.
Applicable tax is calculated in the cart.
Refund policy
Included: Access to this course’s published lessons for the period shown above.
Live sessions, reviewed assignments and online labs are available only where explicitly included or assigned.