Curriculum in preparation

Learn FPGA Partial Reconfiguration / Dynamic Function Exchange (DFX) for run-time hardware flexibility. Covers static vs reconfigurable partition design, decoupling logic, partial bitstream generation, ICAP interface, and PR use cases in software-defined radio and adaptive computing.

Curriculum in preparation

Implement and verify PCIe on FPGA using vendor IP cores. Covers Xilinx PCIe IP configuration, BAR design, DMA controller integration, interrupt handling, PCIe compliance testing, and in-system debug with PCIe protocol analysers. Hands-on DMA engine implementation on Xilinx UltraScale+ hardware.

Curriculum in preparation

Learn FPGA-based ASIC prototyping for pre-silicon software validation. Covers FPGA partitioning strategies, TDM for inter-FPGA connectivity, prototype bring-up methodology, debug insertion, and SW/FW validation on FPGA prototypes using Synopsys HAPS and Xilinx VU19P platforms.

Curriculum in preparation

Accelerate hardware design with High-Level Synthesis using Xilinx Vitis HLS. Covers C/C++ to RTL synthesis, pipeline and dataflow optimisation pragmas, memory partitioning, AXI interface synthesis, and co-simulation. Projects implement ML inference accelerators and DSP kernels for FPGA acceleration.

Curriculum in preparation

Master FPGA timing constraint methodology for clean timing closure. Covers XDC constraint creation, CDC constraint handling, I/O timing, multi-clock designs, and timing closure debugging in Vivado Timing Analyser. Directly applicable to real-product FPGA designs.

Curriculum in preparation

Bridge RTL design with FPGA implementation. Covers FPGA-specific RTL coding styles, resource-aware synthesis, mapping to BRAM/DSP primitives, timing closure methodology, and FPGA-to-ASIC migration. Projects implement AXI-connected signal processing blocks on Xilinx UltraScale FPGA hardware.

Curriculum in preparation

Learn the end-to-end FPGA design flow using Xilinx Vivado and Intel Quartus Prime. Covers RTL simulation, synthesis, technology mapping, placement, routing, timing constraint entry, bitstream generation, and in-system debug (ILA/SignalTap) on real Xilinx Artix-7 and Intel Cyclone V boards.

Available now · Self-paced

Start your FPGA journey with a comprehensive look at FPGA architecture and fundamentals. Covers CLBs, LUTs, flip-flops, BRAM, DSP blocks, clock resources, and IO banks for Xilinx UltraScale+ and Intel Agilex FPGAs. Ideal for ECE graduates and software engineers transitioning into FPGA roles.