In short: Photolithography transfers a mask pattern into resist through a fixed sequence — substrate prep and HMDS priming, spin coating, soft bake, alignment and exposure, post-exposure bake, development, and hard bake — where each step controls a specific physical variable (film thickness, solvent content, acid diffusion, dissolution contrast) that together set the final critical dimension.
Photolithography is the step a modern fab repeats more than any other — a 7 nm logic flow runs 60 to 80 litho layers, and every one of them follows the same ordered recipe. Skip a bake or overshoot a dose and the pattern either collapses or never resolves. This article walks the sequence end to end, explains why each step exists, and gives the numbers and tool context an engineer is expected to know in an interview. For the chemistry of the develop puddle specifically, see our deep dive on the photoresist develop step.
Why the order is fixed
Each operation sets up a boundary condition for the next. Soft bake drives off casting solvent so the resist is mechanically stable enough to make contact or proximity exposure without sticking to the mask; if too much solvent remains, the photoacid generator (PAG) behaves unpredictably during exposure. The post-exposure bake (PEB) then drives the acid-catalysed deprotection reaction in a chemically amplified resist — do it before exposure and there is no latent acid image to amplify. The sequence is not a convention; it is dictated by the physics of solvent removal, latent-image formation, and dissolution contrast.
Step 1 — Substrate prep and HMDS priming
Silicon and oxide surfaces are hydrophilic; a monolayer of adsorbed water lifts resist and causes pattern peeling during development. Vapour-phase hexamethyldisilazane (HMDS) in a prime oven converts surface silanol (Si–OH) groups to hydrophobic Si–O–Si(CH₃)₃, giving the resist a dry, high-contact-angle surface to bond to. A typical prime runs 60–120 s at 120–150 °C. Skipping it is the single most common cause of "resist lifting" defects in a student fab.
Step 2 — Spin coating
A fixed volume of resist (say 3–5 mL) is dispensed onto the wafer, which then spins at 2,000–6,000 rpm. Final thickness follows the classic relation t ∝ ω⁻¹ᐟ² — halving thickness roughly requires quadrupling spin speed — modulated by resist viscosity and solids content. A 1.0 µm i-line resist might spin at 3,500 rpm; a thin EUV resist of 30–50 nm needs a low-viscosity formulation. Edge-bead removal (EBR) solvent trims the thick rim so the wafer seats flat in later chucks.
Key fact: Spin-coating uniformity is normally held to better than ±1% (1σ) across a 300 mm wafer. Non-uniformity directly becomes dose error at exposure, since thicker resist needs more energy to clear.
Step 3 — Soft bake (pre-bake)
The coated wafer bakes on a hotplate, typically 90–110 °C for 60–90 s. This removes 80–90% of the casting solvent, improving adhesion and stabilising the film. Under-baking leaves solvent that bubbles during exposure and smears the latent image; over-baking can prematurely decompose the PAG and lower sensitivity. Soft-bake temperature is a tuned recipe parameter, not a fixed constant.
Step 4 — Alignment and exposure
The wafer is aligned to the previous layer using alignment marks, then exposed. The resolution is bounded by the Rayleigh criterion, CD = k₁·λ/NA. Here λ is the wavelength (365 nm i-line, 193 nm ArF, 13.5 nm EUV), NA the numerical aperture, and k₁ a process factor pushed as low as ~0.28 with resolution-enhancement techniques. This is why the industry marched from i-line steppers to 193 nm immersion scanners (ASML) and then to EUV. Mask synthesis and OPC are handled in tools such as Synopsys Proteus or Siemens Calibre, and the resist/optics interaction is modelled in Synopsys Sentaurus Lithography.
| Source | Wavelength | Typical CD reach | Era |
|---|---|---|---|
| i-line (Hg) | 365 nm | ~350 nm | late 1990s |
| KrF | 248 nm | ~150 nm | early 2000s |
| ArF immersion | 193 nm | ~38 nm (SADP) | 2007+ |
| EUV | 13.5 nm | ~13 nm | 2019+ |
Step 5 — Post-exposure bake (PEB)
In a chemically amplified resist the exposure only creates acid where photons landed. PEB (typically 100–130 °C, 60–90 s) drives that acid to catalyse deprotection of the polymer, flipping its solubility. PEB also smooths standing-wave ridges caused by thin-film interference in the resist. PEB temperature control is brutal: a 1 °C drift can shift CD by several nanometres, which is why scanners and tracks (TEL, SCREEN) hold hotplate zones to ±0.1 °C. Acid diffusion length during PEB is itself a resolution limiter at the leading edge.
Key fact: PEB sensitivity is often the dominant CD-uniformity knob — many fabs budget tighter tolerance on PEB temperature than on exposure dose because of the catalytic amplification gain.
Step 6 — Development
A puddle of developer — almost universally 2.38% tetramethylammonium hydroxide (TMAH) — dissolves the soluble regions. For a positive resist the exposed areas wash away; for negative resist the unexposed areas do. Dissolution contrast (the sharpness of the solubility transition) determines sidewall angle and resolution. Puddle time is on the order of 30–60 s, followed by a deionised-water rinse and spin-dry. The full chemistry, surfactant effects, and defect modes are covered in our companion piece on the photoresist develop step.
Step 7 — Hard bake (post-bake)
A final bake, often 110–140 °C for 60–120 s, hardens the patterned resist, drives out residual developer and water, and improves etch and implant resistance. Too hot and the features reflow and round off, degrading CD; the hard-bake window is a trade-off between mechanical robustness and pattern fidelity. After hard bake the wafer moves to etch or ion implant, where the resist acts as the physical mask.
Inspection and the loop back
After develop (ADI) and again after etch (AEI), CD-SEM metrology and overlay checks confirm the pattern is in spec. If not, the resist is stripped and the whole sequence reruns — "rework" — which is why keeping every bake and dose centred matters economically, not just technically. A single relithography on a 300 mm wafer costs real money and cycle time.
Learning this flow hands-on is the fastest way to internalise it. Our CourseTron nanofabrication courses run a full process flow in simulation, and for a production-grade VLSI design track our training partner ChipXpert VLSI training covers the mask-design side that feeds this flow.
Want to run spin-speed, dose, and bake trade-offs yourself? Join the CourseTron Nano Fab course and build an end-to-end lithography recipe in our interactive simulator.
Frequently asked questions
Why is soft bake done before exposure and not after?
Soft bake removes casting solvent so the film is dimensionally stable and the photoacid generator responds predictably. Residual solvent during exposure degrades the latent image, so the bake must precede the light step.
What is the difference between soft bake, PEB, and hard bake?
Soft bake removes solvent after coating; post-exposure bake drives the acid-catalysed deprotection that forms the developable image and smooths standing waves; hard bake hardens the final pattern for etch or implant. Three different purposes, three different points in the flow.
Why is 2.38% TMAH the standard developer?
It is a metal-ion-free base that gives reproducible dissolution of deprotected novolac/acrylate resists with high contrast and no sodium or potassium contamination, which would poison transistors.
Does EUV lithography use the same step sequence?
Yes — prime, coat, soft bake, expose, PEB, develop, hard bake all remain, though EUV adds vacuum handling, much thinner resist, and tighter dose/PEB control. The ordering is unchanged.