VLSI Glossary — 150+ Chip Design Terms Explained

Bookmark this page — it covers the vocabulary of the full chip-design flow, from RTL to GDSII and beyond. Educators, bloggers and authors may cite these definitions with attribution and a link to CourseTron.

Digital Design Fundamentals

RTL (Register Transfer Level)

A hardware description style that models a circuit as data transfers between registers on clock edges, written in Verilog, SystemVerilog or VHDL.

HDL (Hardware Description Language)

A programming language for describing digital hardware — Verilog, SystemVerilog and VHDL are the industry standards.

Verilog

The most widely used HDL for RTL design, standardized as IEEE 1364.

SystemVerilog

An extension of Verilog (IEEE 1800) adding advanced verification constructs — classes, constrained randomization, assertions and coverage.

VHDL

A strongly typed HDL (IEEE 1076) common in aerospace, defense and European industry.

Netlist

A gate-level description of a circuit: the logic cells used and how they interconnect, produced by synthesis.

Flip-flop

An edge-triggered storage element that captures its input on a clock edge — the basic sequential building block.

Latch

A level-sensitive storage element, transparent while its enable is active; used deliberately in some designs and accidentally created by bad RTL.

FSM (Finite State Machine)

A sequential circuit that moves between defined states based on inputs — the standard way to model control logic.

Combinational logic

Logic whose output depends only on current inputs (gates, muxes, adders) — no storage.

Sequential logic

Logic whose output depends on current inputs and stored state, driven by a clock.

Mux (Multiplexer)

A selector that routes one of several inputs to the output based on a select signal.

Decoder / Encoder

Circuits converting between binary codes and one-hot signal lines.

FIFO (First-In First-Out)

A queue buffer used to pass data between logic blocks, often across clock domains; depth sizing prevents overflow and underflow.

Clock domain

A region of logic driven by one clock. Signals crossing between domains need special synchronization.

CDC (Clock Domain Crossing)

Any signal path between different clock domains; handled with synchronizers, handshakes or async FIFOs to avoid metastability.

Metastability

An unstable flip-flop state, caused by violating setup/hold timing, where the output hovers between 0 and 1 for an unpredictable time.

Synchronizer

Typically two back-to-back flip-flops that let a signal safely cross into a new clock domain.

Setup time

The minimum time a flip-flop's data input must be stable before the clock edge.

Hold time

The minimum time data must remain stable after the clock edge.

Pipeline

Splitting a long logic path into stages separated by registers to raise clock frequency and throughput.

Datapath

The portion of a design that processes data — ALUs, multipliers, shifters — as opposed to control logic.

ISA (Instruction Set Architecture)

The programmer-visible contract of a processor — its instructions, registers and memory model (e.g. RISC-V, ARM, x86).

RISC-V

An open, royalty-free ISA widely used in modern processor design and education.

SoC (System on Chip)

A chip integrating processors, memory, interconnect and peripherals into one silicon die.

IP core

A pre-designed, reusable block (CPU, USB controller, SRAM) licensed or reused across chips.

AMBA / AXI

ARM's on-chip bus protocol family; AXI is the dominant high-performance interconnect standard in SoCs.

NoC (Network on Chip)

A packet-based on-chip interconnect that replaces buses in large SoCs, using routers and links.

Verification

Testbench

The simulation environment that drives stimulus into a design and checks its outputs.

DUT (Design Under Test)

The RTL block being verified inside a testbench.

UVM (Universal Verification Methodology)

The industry-standard SystemVerilog class library for building reusable, constrained-random testbenches.

Constrained-random verification

Generating randomized stimulus within legal constraints to hit corner cases directed tests would miss.

Functional coverage

User-defined metrics recording which interesting scenarios the tests have actually exercised.

Code coverage

Automatic metrics (line, toggle, branch, FSM) showing which RTL the simulation executed.

Assertion (SVA)

A formal statement of expected behavior (SystemVerilog Assertions) checked continuously during simulation or formally proven.

Scoreboard

The testbench component that compares DUT output against a reference model's expected output.

Monitor / Driver / Sequencer

UVM agent components: the driver wiggles DUT pins from transactions, the monitor observes pins into transactions, the sequencer feeds the driver stimulus.

Regression

Running the full test suite (often thousands of seeds) repeatedly to catch new bugs after changes.

Formal verification

Mathematically proving properties of a design for all possible inputs, without simulation vectors.

Equivalence checking (LEC)

Formally proving two versions of a design (e.g. RTL vs post-synthesis netlist) are logically identical.

Emulation

Running a design on specialized hardware (Palladium, Zebu, Veloce) orders of magnitude faster than simulation for software bring-up.

Gate-level simulation (GLS)

Simulating the synthesized netlist, often with SDF timing, to verify reset, X-propagation and timing behavior.

X-propagation

How unknown (X) values spread through simulation; X-optimism/pessimism can hide or exaggerate real bugs.

Sanity / smoke test

A quick minimal test run first to confirm the environment and basic function before full regression.

Physical Design

Physical design (PD)

The back-end flow converting a netlist into manufacturable geometry: floorplan → place → CTS → route → signoff.

Floorplanning

Deciding die size, macro placement, pin locations and power structure before placement.

Macro

A large pre-designed block (SRAM, PLL, IP) placed as one unit during floorplanning.

Standard cell

A pre-characterized logic gate of fixed height from the foundry library, tiled in rows.

Placement

Assigning locations to all standard cells, optimizing timing, congestion and wirelength.

CTS (Clock Tree Synthesis)

Building the buffered network that delivers the clock to every flip-flop with minimal skew and acceptable latency.

Clock skew

The arrival-time difference of the same clock edge at different flip-flops.

Routing

Connecting placed cells with metal wires across multiple layers, meeting design rules.

Congestion

Local shortage of routing tracks; causes detours, DRCs and timing degradation.

GDSII / GDS

The final layout database format delivered to the foundry — hence "RTL to GDSII."

LEF/DEF

Exchange formats: LEF describes library/technology geometry; DEF carries a design's placement and routing.

Power grid / PDN

The metal mesh distributing VDD/VSS across the die; must meet IR-drop and EM limits.

IR drop

Voltage loss across the power network under current load; excessive drop slows or breaks logic.

Electromigration (EM)

Gradual metal atom displacement in wires under high current density — a long-term reliability limit.

DRC (Design Rule Check)

Verifying layout geometry obeys the foundry's manufacturing rules.

LVS (Layout vs Schematic)

Verifying the drawn layout electrically matches the netlist.

Antenna effect

Charge buildup on long metal during fabrication that can damage gate oxide; fixed with diodes or metal jumping.

Filler cells / decap

Cells filling empty row space; decaps add local charge storage to stabilize the supply.

Tap cell / endcap

Cells providing well/substrate connections and proper row terminations required by the library.

Utilization

The fraction of core area occupied by cells; too high causes routing congestion.

ECO (Engineering Change Order)

A late, targeted netlist/layout change — often via spare cells or metal-only edits — avoiding a full re-run.

Spare cells

Unused gates sprinkled in layout so late fixes can be wired with metal-only mask changes.

Double patterning

Splitting one layout layer across two masks to print features finer than lithography allows in one pass.

Timing & STA

STA (Static Timing Analysis)

Exhaustively checking all timing paths against constraints without simulation — the signoff method for timing.

Critical path

The slowest register-to-register path, which limits maximum clock frequency.

Slack

Required time minus arrival time on a path; negative slack is a timing violation.

SDC (Synopsys Design Constraints)

The standard file format specifying clocks, I/O delays, false paths and exceptions.

False path

A structurally present path that can never affect real operation, excluded from timing analysis.

Multicycle path

A path intentionally allowed more than one clock cycle to propagate.

Setup violation

Data arriving too late before the capture clock edge — limits frequency; fixed by speeding the path or relaxing the clock.

Hold violation

Data changing too soon after the clock edge — breaks the chip at ANY frequency; fixed with delay buffers.

OCV / AOCV / POCV

Margining methods modeling on-chip process variation in timing analysis, from flat derates to statistical models.

Corner (PVT)

A process/voltage/temperature combination at which timing is analyzed (e.g. SS 0.72V 125°C).

Timing closure

The iterative process of fixing all setup/hold violations across all corners and modes.

Clock gating

Disabling the clock to idle registers via a gating cell to save dynamic power.

Latency (clock)

Delay from the clock source to a flip-flop's clock pin; source + network latency.

Jitter

Cycle-to-cycle variation in clock edge timing, subtracted from the usable clock period.

Derate

A multiplier applied to cell/net delays to model variation pessimistically in STA.

CPPR / CRPR

Removing artificially double-counted pessimism on the common portion of launch and capture clock paths.

Low Power

Dynamic power

Power consumed by switching activity — proportional to C·V²·f.

Leakage (static) power

Power drawn by transistors even when idle; grows at smaller nodes and higher temperature.

Power gating

Shutting off supply to idle blocks with sleep switches; state may be retained in special registers.

Multi-voltage design

Running different blocks at different supply voltages to trade performance versus power.

Level shifter

A cell translating signals between voltage domains safely.

Isolation cell

A cell clamping outputs of a powered-down domain so floating values can't corrupt live logic.

Retention register

A flip-flop with a shadow latch that keeps state while its domain is power-gated.

UPF (Unified Power Format)

The IEEE 1801 standard describing power intent — domains, supplies, isolation, retention — to the whole flow.

DVFS

Dynamic Voltage and Frequency Scaling — adjusting V and f at runtime to match workload and save energy.

Vt flavors (HVT/SVT/LVT)

Threshold-voltage variants of the same cell: high-Vt leaks less but is slower; low-Vt is faster but leaky. Mixing them tunes power/timing.

DFT & Test

DFT (Design for Test)

Structures added to a chip so manufacturing defects can be detected efficiently on a tester.

Scan chain

Flip-flops stitched into shift registers so internal state can be loaded and observed through a few pins.

ATPG

Automatic Test Pattern Generation — tools computing input patterns that expose modeled faults.

Stuck-at fault

The classic fault model: a node behaving as permanently 0 or 1.

Transition / at-speed fault

Fault models catching defects that only fail at full clock speed.

Fault coverage

Percentage of modeled faults the pattern set can detect — a key quality metric.

BIST

Built-In Self-Test — on-chip logic (commonly for memories, MBIST) that tests itself without external patterns.

Boundary scan / JTAG

IEEE 1149.1 serial access ring around chip pins for board-level test and debug access.

Scan compression

On-chip decompressors/compactors reducing tester time and data volume versus plain scan.

Burn-in

Stressing parts at elevated voltage/temperature to weed out early-life failures.

Yield

The fraction of manufactured dies that pass all tests.

ATE

Automatic Test Equipment — the machines that run test patterns against each manufactured chip.

Analog & Mixed-Signal

CMOS

Complementary MOS — the dominant technology pairing NMOS and PMOS transistors for low static power logic.

Threshold voltage (Vt)

The gate voltage at which a MOSFET effectively turns on.

PLL (Phase-Locked Loop)

A feedback circuit generating a stable high-frequency clock locked to a reference.

ADC / DAC

Converters between analog signals and digital codes; resolution (bits) and speed define quality.

LDO

Low-DropOut regulator — an on-chip linear voltage regulator for clean local supplies.

Bandgap reference

A circuit producing a supply- and temperature-stable reference voltage (~1.2 V).

SerDes

Serializer/Deserializer — very high-speed serial link circuits (PCIe, Ethernet, USB PHYs).

Op-amp

A high-gain differential amplifier — the workhorse analog building block.

Layout matching

Analog layout techniques (common centroid, interdigitation, dummies) making paired devices behave identically.

Mixed-signal

Designs combining analog and digital circuits on one die, with careful isolation between them.

Signal integrity (SI)

Keeping signals clean against crosstalk, reflection and attenuation, on-chip and on-board.

Power integrity (PI)

Keeping supply voltage stable against switching noise across chip, package and board.

Fabrication & Technology

Wafer

The thin silicon disc (typically 300 mm) on which hundreds of dies are fabricated together.

Die

One individual chip cut from the wafer.

Foundry

A company that manufactures chips designed by others (TSMC, Samsung Foundry, GlobalFoundries).

Fabless

A company that designs chips but outsources manufacturing (NVIDIA, Qualcomm, AMD).

Process node

The technology generation label (7nm, 5nm, 3nm) — smaller nodes give denser, faster, lower-power transistors.

Photolithography

Printing circuit patterns onto wafers by exposing photoresist through masks.

EUV

Extreme Ultraviolet lithography (13.5 nm light) enabling patterning at 7nm-class nodes and below.

Mask / reticle

The patterned plate through which each layer is exposed; a full mask set costs millions at advanced nodes.

Etching

Removing material selectively (plasma/chemical) to transfer the printed pattern into the wafer.

Deposition (CVD/PVD/ALD)

Adding thin films of insulators and metals layer by layer.

Ion implantation

Firing dopant ions into silicon to create transistor regions.

CMP

Chemical-Mechanical Planarization — polishing each layer flat before the next.

FinFET

A 3D transistor whose gate wraps a silicon fin — standard from ~16nm to 5nm.

GAA (Gate-All-Around)

Nanosheet transistors fully surrounded by gate — the successor to FinFET at 3nm/2nm.

FEOL / BEOL

Front-End-Of-Line (transistors) versus Back-End-Of-Line (metal interconnect) portions of fabrication.

Packaging

Enclosing and connecting the die to the outside world — from wire-bond to flip-chip to advanced 2.5D/3D.

Chiplet

Splitting a system across multiple smaller dies integrated in one package (UCIe is the emerging interconnect standard).

Interposer / 2.5D

A silicon or organic substrate carrying multiple dies side by side with dense interconnect (e.g. HBM beside GPU).

Wafer sort / final test

Testing dies on-wafer before packaging, then again after packaging.

PDK (Process Design Kit)

The foundry's package of models, rules and libraries enabling design in a given process.

EDA & Flow

EDA (Electronic Design Automation)

The software industry (Synopsys, Cadence, Siemens EDA) providing chip design tools.

Synthesis

Compiling RTL into an optimized gate-level netlist against timing constraints (Design Compiler, Genus).

Place & route tool

The physical implementation platform (Innovus, IC Compiler II / Fusion Compiler).

Signoff

The final independent checks — STA (PrimeTime/Tempus), physical verification (Calibre), power (Voltus/RedHawk) — before tapeout.

Tapeout

Releasing the final verified GDSII to the foundry — the finish line of the design flow.

Simulator

Event-driven HDL execution engines: VCS, Xcelium, Questa.

Liberty (.lib)

The file format characterizing cell timing/power used by synthesis and STA.

SDF

Standard Delay Format — annotates real delays onto gate-level simulation.

Tcl

The scripting language driving virtually every EDA tool; essential for flow automation.

Flow

The scripted sequence of tools and checks taking a design from spec to GDSII reproducibly.

Milkyway / NDM / OA

Tool-specific physical design databases used by implementation platforms.

Cross-probing

Selecting an object in one view (netlist/layout/schematic) and seeing it highlighted in another.

Keep learning

Definitions get you started — fluency comes from using these concepts inside real tool flows. Browse all courses across VLSI, verification, physical design, embedded and FPGA, start with the online electronics classes overview, or test yourself with free mock tests. See also the VLSI Salary Report 2026.

Frequently Asked Questions

Can I use these definitions in my article, thesis or course material?

Yes — cite "CourseTron VLSI Glossary" with a link to this page. The definitions are written for accuracy and plain-English clarity, and we keep them updated.

Which terms should a fresher learn first?

Start with the digital fundamentals (RTL, setup/hold, FSM, CDC), then the vocabulary of the domain you're targeting — UVM and coverage for verification; floorplan-to-signoff terms for physical design.

How is this glossary different from a textbook index?

Each entry is a working engineer's definition — what the term means in practice in an industry flow — rather than a formal academic treatment. It's designed for interview prep and on-the-job orientation.