In short: A MOSFET is built bottom-up on a silicon wafer by forming doped wells, growing a thin high-quality gate oxide, patterning the polysilicon gate, and finally self-aligning the source/drain implants to that gate — each step governed by thermal budget, alignment, and dopant control.
The metal-oxide-semiconductor field-effect transistor (MOSFET) is the workhorse of every modern chip, from a 28 nm microcontroller to a 3 nm mobile SoC. Understanding how one is physically built is essential for anyone moving into process integration, device engineering, or physical design. This article walks through the classic planar front-end-of-line (FEOL) flow: well formation, gate oxide growth, poly gate patterning, and source/drain implantation — explaining not just the sequence but the reasons each step is done the way it is.
1. Starting Material and Isolation
Fabrication begins with a lightly doped, defect-free single-crystal silicon wafer, typically p-type with a boron background of roughly 1015 cm-3 and a <100> orientation. Before any transistor can be defined, neighbouring devices must be electrically isolated. In processes below ~0.25 µm this is done with Shallow Trench Isolation (STI): trenches 300–400 nm deep are etched, lined with a thin thermal oxide, filled with CVD oxide, and planarised by chemical-mechanical polishing (CMP). STI replaced the older LOCOS "bird's beak" approach because it packs devices far more densely.
Why orientation matters: <100> silicon is chosen because its Si–SiO2 interface has the lowest density of trap states (Dit), which directly improves channel mobility and threshold-voltage stability.
2. Well Formation
A CMOS chip needs both NMOS and PMOS transistors. NMOS devices sit in a p-well; PMOS devices sit in an n-well. These wells are created by high-energy ion implantation through a patterned photoresist mask, so the dopants land only where intended. A twin-well flow implants phosphorus (for the n-well, ~1017–1018 cm-3) and boron (for the p-well) in separate masking steps.
After implantation, a high-temperature drive-in anneal (often 1000–1100 °C) diffuses and electrically activates the dopants, repairing lattice damage from the implant. Engineers also add a shallower "VT-adjust" implant here to set the threshold voltage precisely, and an "anti-punchthrough" implant deeper down to suppress leakage between source and drain. Modern process design kits (PDKs) from foundries let designers model these profiles in TCAD tools such as Synopsys Sentaurus before silicon is ever committed.
3. Gate Oxide Growth
The gate dielectric is the most critical film in the whole device — it is literally the capacitor plate that lets the gate control the channel. It is grown, not deposited, by thermal oxidation in a furnace or rapid-thermal processor, because a grown SiO2 gives the cleanest, lowest-defect Si–SiO2 interface. Dry oxidation (Si + O2 → SiO2) is used for thin gate oxides because it is slow and highly controllable.
Scaling drives this layer astonishingly thin. A 0.18 µm node used roughly 3–4 nm of oxide; by 90 nm it was ~1.2 nm — only a handful of atomic layers — at which point quantum tunnelling leakage became intolerable. The industry responded by replacing SiO2 with high-κ dielectrics such as hafnium oxide (HfO2) paired with a metal gate (the "high-κ/metal-gate" or HKMG stack, introduced by Intel at 45 nm), which gives the same capacitance with a physically thicker, lower-leakage film.
Equivalent Oxide Thickness (EOT): High-κ layers are quoted as an EOT — the thickness of SiO2 that would give the same capacitance. A 2 nm HfO2 film (κ≈20) can achieve an EOT below 1 nm while leaking orders of magnitude less current.
4. Polysilicon Gate Patterning
A blanket layer of polysilicon (typically 100–200 nm) is deposited over the gate oxide by low-pressure CVD and heavily doped to make it conductive. The gate is then defined lithographically: photoresist is spun on, exposed through a reticle on a 193 nm immersion or EUV scanner, developed, and used as an etch mask. A highly anisotropic plasma (reactive-ion) etch transfers the pattern straight down, producing near-vertical gate sidewalls.
The gate length — the dimension that names the technology node — is the single most dimension-critical feature on the chip, so line-edge roughness and critical-dimension (CD) uniformity are tracked obsessively. After the gate is etched, thin dielectric spacers (silicon nitride or oxide) are formed on its sidewalls; these will set the offset for the subsequent heavy source/drain implant and are what make the process self-aligned.
5. Source/Drain Implantation
With the gate in place, the heavily doped source and drain are implanted. For NMOS, arsenic or phosphorus forms n+ regions (>1020 cm-3); for PMOS, boron or BF2 forms p+ regions. The key insight is self-alignment: the polysilicon gate itself masks the channel, so the source and drain edges line up with the gate automatically, eliminating overlap capacitance from mask misalignment.
Before the heavy implant, a shallow, lightly doped drain (LDD) extension is implanted right at the gate edge to spread the electric field and suppress hot-carrier degradation. After all implants, a rapid thermal anneal (RTA, ~1050 °C for a few seconds, or millisecond laser anneal at advanced nodes) activates the dopants while keeping the thermal budget tiny so the junctions stay shallow. Finally, a self-aligned silicide ("salicide", e.g. NiSi) is formed on the exposed source, drain, and gate to cut contact resistance.
Thermal budget — the hidden constraint
Every anneal diffuses previously placed dopants. Because of this, the flow is ordered from highest to lowest temperature: deep wells first, source/drain last. This is why you cannot simply reorder steps — the thermal budget is a shared, finite resource across the whole FEOL.
| Step | Dopant / Film | Typical concentration / thickness | Peak temperature |
|---|---|---|---|
| Well implant | B (p-well), P (n-well) | ~1017 cm-3 | 1000–1100 °C drive-in |
| Gate oxide | SiO2 / HfO2 | 1–4 nm (EOT <1 nm at HKMG) | ~800–900 °C |
| Poly gate | Doped polysilicon | 100–200 nm | ~600 °C (LPCVD) |
| Source/drain | As/P (n+), B (p+) | >1020 cm-3 | ~1050 °C RTA (seconds) |
Modern nodes extend this planar baseline into 3D FinFET and gate-all-around (GAA) nanosheet geometries, but the conceptual order — isolate, well, gate dielectric, gate, self-aligned source/drain — survives intact. If you want to see how these steps are sequenced into a full complementary flow, read our companion piece on CMOS fabrication steps, and for the dopant physics itself see ion implantation explained.
Want to run these flows hands-on in Sentaurus TCAD and see device curves fall out? The Nano Fab track on CourseTron courses takes you from bare wafer to extracted I–V. Teams needing production silicon support can also explore Avecas VLSI design services.
Frequently Asked Questions
Why is the gate oxide grown instead of deposited?
Thermal oxidation consumes the top layer of the silicon itself, producing an atomically clean Si–SiO2 interface with very few trap states. A deposited oxide would sit on top of a contaminated surface and ruin channel mobility and reliability.
What makes a MOSFET process "self-aligned"?
The polysilicon gate (plus its sidewall spacers) acts as the implant mask for the source and drain. Because the same physical feature defines both the channel and the implant edges, they align perfectly regardless of mask overlay error — removing a major source of parasitic capacitance.
Why implant the wells before growing the gate oxide?
Well formation needs a high-temperature drive-in anneal. Doing it after the ultra-thin gate oxide and shallow source/drain junctions existed would diffuse and destroy them. Steps are ordered from highest thermal budget to lowest.
What replaced SiO2 at advanced nodes?
Below ~45 nm, high-κ dielectrics like hafnium oxide combined with metal gates (HKMG) replaced SiO2/polysilicon, giving the same gate capacitance with far less tunnelling leakage.