In short: Multi-chip modules and advanced packaging place several dies side-by-side or stacked inside one package, linked by silicon interposers, bridges, or hybrid bonds, so you get the density and bandwidth of a big monolithic chip without paying its yield and reticle penalties.
Why a single big die stopped being the answer
For decades the recipe was simple: shrink the transistor, grow the die, integrate everything on one piece of silicon (an SoC). Two walls broke that recipe. First, the lithography reticle limit caps a single exposure at roughly 858 mm² (about 26 mm × 33 mm), so a design larger than that physically cannot be printed as one die. Second, yield falls off a cliff with area: at a defect density of, say, 0.1 defects/cm², a 800 mm² die yields far worse than four 200 mm² dies, because one killer defect scraps the whole monolith but only one quarter of a partitioned design.
The fix is to disaggregate: split the function into smaller dies, manufacture each on the process node that suits it, and reassemble them in a package. That is what a multi-chip module (MCM) does, and what "advanced packaging" refers to when the interconnect between those dies approaches on-chip density. The dies themselves are often called chiplets — see our deeper dive on chiplet architecture explained.
Key fact: AMD's EPYC server CPUs assemble up to 12 compute chiplets built on TSMC 5 nm around a single I/O die built on a cheaper 6 nm node — mixing process generations in one package is a cost lever you simply cannot pull with a monolithic die.
The packaging spectrum: 2D, 2.5D, and 3D
It helps to sort the techniques by how the dies are arranged and how they talk to each other.
- 2D MCM — dies sit side-by-side on an organic laminate substrate and connect through package traces. Cheap and mature, but the wires are long (millimetres) so bandwidth and energy-per-bit are limited.
- 2.5D — dies sit on a silicon interposer whose fine wiring (sub-micron pitch) routes thousands of signals between them. This is how GPUs attach High-Bandwidth Memory (HBM): TSMC's CoWoS (Chip-on-Wafer-on-Substrate) is the canonical example.
- 3D — dies are stacked vertically and joined by through-silicon vias (TSVs) or copper-to-copper hybrid bonding. The vertical path is tens of microns instead of millimetres, which is the shortest, fastest, lowest-energy link available. AMD's 3D V-Cache stacks an SRAM die directly on the CPU core die this way.
Where the bandwidth actually comes from
Bandwidth is just wires times frequency. A monolithic chip talking to a separate memory chip over a PCB is throttled by how many pins the package can afford and how fast you can switch a long, capacitive board trace. Advanced packaging attacks both terms.
Take HBM3 as a concrete example. It exposes a 1024-bit-wide interface per stack running near 6.4 Gbps per pin — that is roughly 819 GB/s from a single memory stack. You could never route 1024 data lines across a PCB to a memory module at that speed; the signal integrity and pin count are impossible. On a silicon interposer, those 1024 traces are a few millimetres long with controlled impedance, so the link closes easily. An NVIDIA H100-class GPU pairs its logic die with several HBM stacks over CoWoS to reach multiple terabytes per second of memory bandwidth.
Key fact: Moving a bit across a long PCB trace can cost 10–20 pJ; a 2.5D interposer link is roughly 1–2 pJ/bit, and a 3D hybrid-bonded link can drop below 0.1 pJ/bit. Shorter wires are not just faster — they are an order of magnitude more energy-efficient.
Interconnect: bumps, bridges, and bonds
The physical joint between dies defines the whole class of technology.
| Technique | Bump / pitch | Typical use | Example |
|---|---|---|---|
| Flip-chip C4 | ~100–150 µm | Die-to-substrate | Classic MCM |
| Microbump (2.5D/3D) | ~40–55 µm | Die-to-interposer | CoWoS, HBM |
| Silicon bridge | ~45 µm | Local high-density link | Intel EMIB |
| Hybrid bond (Cu-Cu) | <10 µm, toward 1 µm | 3D stacking | AMD 3D V-Cache, SoIC |
Intel's EMIB deserves a note: instead of a full (expensive) silicon interposer, it embeds a small silicon bridge chip only where two dies need a dense connection, leaving the rest of the package on cheap organic substrate. It is a pragmatic middle path between 2D and full 2.5D.
How you design one: EDA and standards
A multi-die package is co-designed, not thrown together at assembly. The interposer or substrate is itself a routing problem with power-delivery and thermal constraints spanning all the dies. Tool flows have grown to match: Synopsys 3DIC Compiler, Cadence Integrity 3D-IC, and Siemens Calibre 3DSTACK / xACT handle multi-die floorplanning, die-to-die routing, and — critically — cross-die LVS and thermal analysis, because a hotspot in a stacked die can only escape through its neighbours.
On the protocol side, UCIe (Universal Chiplet Interconnect Express) standardises the die-to-die link so chiplets from different vendors can interoperate, much as PCIe did for boards. If you are moving from board-level to package-level integration, our course on advanced packaging design flow walks through the full co-design loop, and teams needing production tape-out support often lean on specialist VLSI design services for the interposer sign-off.
The trade-offs nobody should skip
Advanced packaging is not free density. Three costs dominate. Thermal: stacking dies concentrates power; a logic die under a memory stack must conduct heat through the stack, so power maps and TSV placement become thermal-design decisions. Known-good-die testing: if you bond a bad die into an expensive stack, you scrap the whole assembly, so each chiplet must be tested before assembly — this is why wafer-level and KGD test flows matter more than ever. Mechanical: mismatched coefficients of thermal expansion between silicon, interposer, and substrate create warpage and stress on the microbumps, a reliability concern Siemens and others model explicitly.
Want to design multi-die systems, not just read about them? CourseTron's Nano Fab track takes you from reticle limits through CoWoS, EMIB, UCIe and 3D-IC sign-off with hands-on Synopsys and Cadence labs. Explore the CourseTron courses →
Frequently asked questions
What is the difference between an MCM and a System-in-Package (SiP)?
An MCM typically integrates homogeneous or logic dies on a shared substrate. SiP is the broader umbrella — it can also include passives, sensors, RF, and memory, i.e. a whole subsystem in one package. All MCMs are SiPs, but not every SiP is a classic MCM.
Is 3D stacking always better than 2.5D?
No. 3D gives the shortest links and best energy-per-bit, but it concentrates heat and complicates test and repair. For logic-plus-HBM systems where memory already runs cool-ish beside the logic, 2.5D on an interposer is often the right and cheaper choice.
What does UCIe standardise?
UCIe defines the physical, protocol, and software layers of the die-to-die interface — bump map, electrical spec, link training, and a protocol stack (it can tunnel PCIe/CXL) — so chiplets from different vendors and foundries can be mixed in one package.
Why not just keep shrinking one big chip?
Two hard limits: the lithography reticle caps die size near 858 mm², and yield drops steeply with area. Partitioning into chiplets sidesteps both and lets each function use its ideal process node.