In short: Turning a bare silicon wafer into a working chip is a loop of deposit-a-layer, pattern-it-with-light, etch-away-the-unwanted, implant-dopants, and wire-it-up-with-metal — repeated hundreds of times until billions of transistors are stacked and interconnected.
A modern logic die packs tens of billions of transistors onto a slab of silicon smaller than a fingernail. Getting there is not one process but a tightly sequenced choreography of physics and chemistry executed in a cleanroom where airborne particle counts are kept thousands of times below a hospital operating theatre. This walkthrough follows a wafer from polished silicon to a finished, testable chip, pausing at the five workhorse stages: deposition, lithography, etch, doping and metallization.
Starting point: the bare wafer
Fabrication begins with a 300 mm monocrystalline silicon wafer sliced from a Czochralski-grown ingot, lapped and polished to a mirror finish flatter than a few nanometres across its whole diameter. Before a single feature is built, the wafer is scrubbed in an RCA clean to strip organics, metals and native oxide — see our companion piece on the wafer cleaning process for why a stray potassium ion can ruin a gate oxide. The clean wafer is the blank canvas; everything that follows adds, removes or transforms thin films on its surface.
Stage 1 — Deposition: building the layers
Every structure on a chip is a stack of thin films, typically 1 nm to a few hundred nanometres thick. Deposition puts those films down. Three families dominate:
- Thermal oxidation grows silicon dioxide by reacting the wafer surface with O₂ or steam at 900–1100 °C. It consumes silicon, so the oxide is exceptionally clean — ideal for gate dielectrics.
- Chemical Vapour Deposition (CVD) reacts gases (silane, TEOS, ammonia) to deposit SiO₂, silicon nitride or polysilicon. LPCVD and PECVD variants trade temperature for conformality.
- Atomic Layer Deposition (ALD) builds films one atomic monolayer per cycle, giving the sub-nanometre thickness control needed for high-k gate stacks such as HfO₂ in FinFET and gate-all-around nodes.
At the 3 nm node the gate dielectric is barely ~10 atoms thick. A one-atom thickness error shifts transistor threshold voltage measurably — which is exactly why ALD, not oxidation, now sets the gate stack.
Stage 2 — Lithography: printing the pattern
Lithography is where design becomes geometry. The wafer is spin-coated with a light-sensitive photoresist, then a projection scanner images a reticle (the mask) onto it, reducing the mask pattern 4× optically. Exposed resist changes solubility; development washes away either the exposed or unexposed regions, leaving a stencil.
The wavelength sets the resolution limit. For a decade the industry pushed 193 nm deep-UV light with immersion and multi-patterning tricks. Leading nodes now use Extreme UV (EUV) at 13.5 nm, generated by blasting tin droplets with a CO₂ laser in vacuum. The design data that drives those masks is prepared with OPC and mask-synthesis tools such as Synopsys Proteus and Siemens Calibre, which pre-distort the layout so the printed shape matches intent despite diffraction.
An EUV scanner from ASML costs well over US$150 million and uses mirrors, not lenses, because almost every material absorbs 13.5 nm light. Lithography is routinely the single most expensive step per layer.
Stage 3 — Etch: carving the structure
With resist defining where to cut, etching removes the exposed film. Two regimes matter:
- Wet etch uses liquid chemistries (HF for oxide, KOH for silicon). It is isotropic — it undercuts in all directions — so it is reserved for non-critical layers and cleaning.
- Dry / plasma etch (RIE) uses reactive ion bombardment to cut straight down, giving the near-vertical sidewalls needed for dense features. A deep-trench or FinFET fin may need an aspect ratio above 30:1 with sidewall deviation under a nanometre.
After etch, the photoresist is stripped and the wafer re-cleaned, ready for the next deposition. The deposit–pattern–etch triad is the fundamental unit of chip building; everything else decorates it.
Stage 4 — Doping: tuning the silicon
Pure silicon barely conducts. Doping deliberately introduces impurities to create the n-type and p-type regions that make transistors work. The dominant method is ion implantation: dopant ions (boron, phosphorus, arsenic) are accelerated to tens or hundreds of keV and fired into the wafer through a patterned mask, so only exposed windows receive dopant. A subsequent rapid thermal anneal (often a millisecond-scale spike anneal) repairs lattice damage and activates the dopants.
| Dopant | Type | Typical role |
|---|---|---|
| Boron (B) | p-type | PMOS source/drain, well |
| Phosphorus (P) | n-type | NMOS lightly-doped drain |
| Arsenic (As) | n-type | Shallow NMOS source/drain |
Implant dose and energy are chosen to place the dopant profile precisely; a few keV changes the junction depth by nanometres, directly affecting leakage and drive current.
Stage 5 — Metallization: wiring it together
Once the transistors exist in silicon, they must be connected. Metallization builds the interconnect stack — today up to 15+ copper layers separated by low-k dielectric. Modern fabs use the dual-damascene flow: etch trenches and vias into the dielectric, line them with a tantalum barrier, electroplate copper to overfill, then planarize with Chemical Mechanical Polishing (CMP) so only the metal inside the trench remains. Repeat per layer.
Lower layers carry dense local signals at minimum pitch; upper layers are thick and wide for power delivery and long global routes. Getting this interconnect RC budget right is a core job of physical-design tools such as Cadence Innovus and Synopsys IC Compiler — the same tools taught in our metallization and interconnect basics primer. Firms that offer end-to-end physical-design and tapeout support, such as Avecas VLSI design services, live and breathe this stage.
Finishing: test, dice and package
After the last metal layer and passivation, the wafer goes to wafer sort, where probe cards electrically test every die; failing dies are inked or mapped out. The wafer is then thinned, diced into individual chips, and the good dies are packaged — wire-bonded or flip-chip bumped — before final test and binning by speed grade.
Want to go from "I know the words" to designing real flows on industry EDA tools? Explore CourseTron's hands-on semiconductor and VLSI courses and build a wafer-to-tapeout mental model that holds up in interviews.
Frequently asked questions
How many process steps does one chip take?
A leading-edge logic chip can require 1,000 or more individual process steps and several hundred lithography layers, with a full fab cycle time of roughly two to three months from bare wafer to tested die.
Why is lithography considered the bottleneck?
Lithography sets the smallest feature you can print, so it caps transistor density. It is also the slowest and most expensive step — an EUV scanner is the most costly tool in the fab — which is why resolution-enhancement and multi-patterning get so much engineering attention.
What is the difference between doping and deposition?
Deposition adds a new film on top of the wafer surface. Doping changes the electrical properties of the silicon itself by driving impurity atoms into the existing lattice — nothing is added as a visible layer.
Why is copper used instead of aluminium for interconnect?
Copper has lower resistivity and far better electromigration resistance than aluminium, so it carries more current in thinner wires with longer lifetime. The trade-off is that copper cannot be plasma-etched easily, which is why the damascene-plus-CMP flow was developed.