Shallow trench isolation (STI)

In short: Shallow trench isolation (STI) electrically separates adjacent transistors by etching sub-micron trenches into silicon and refilling them with CVD oxide, giving planar, compact isolation that replaced LOCOS at the 0.25 µm node and below.

Every modern CMOS chip packs billions of transistors onto a die, and without a reliable way to keep neighbouring devices from leaking current into one another, none of them would work. Shallow trench isolation is the workhorse technique the industry adopted to do exactly that. If you understand STI well, you understand one of the first and most consequential modules in the front-end-of-line (FEOL) flow.

Why isolation matters at all

Place two NMOS transistors side by side in a p-type substrate and you have unintentionally created a parasitic field transistor: the metal or polysilicon running between them acts as a gate, the two diffusions act as source and drain, and the oxide between them is the gate dielectric. If this parasitic device turns on, leakage flows between devices that should be independent. Isolation raises the threshold voltage of that parasitic transistor far above any voltage the circuit will ever see, so it stays firmly off. STI achieves this by physically sinking a thick dielectric plug into the silicon between active regions.

A typical STI trench at a mature node is roughly 250–400 nm deep and lined with a thin thermal oxide before being filled, delivering field thresholds well above the supply rail so the parasitic field device never conducts.

What was wrong with LOCOS

Before STI, the dominant method was LOCOS — LOCal Oxidation of Silicon — where a silicon nitride mask protected the active areas while the exposed field was thermally oxidised into a thick isolation oxide. LOCOS worked beautifully for micron-scale geometries, but it had a fatal scaling flaw: the "bird's beak". Because oxygen diffuses laterally under the nitride edge during the long high-temperature oxidation, the field oxide encroaches into the active area in a tapered wedge. At 0.5 µm that bird's beak might eat 0.2–0.3 µm from each side of a device, which is tolerable. At 0.25 µm it consumes most of your active width. LOCOS also produces non-planar topography that wrecks photolithography depth-of-focus budgets, and it suffers stress-induced defects at the beak. STI eliminates the bird's beak entirely because the isolation boundary is defined by a vertical etched wall, not a creeping oxidation front.

The STI process flow, step by step

A production STI module is a carefully sequenced set of etch, deposition, anneal and polish steps:

• Pad oxide + nitride stack. A thin thermal pad oxide (~10 nm) is grown on the silicon, then a silicon nitride layer (~100–150 nm) is deposited by LPCVD. The nitride is both a hard mask and, crucially, the CMP polish stop.
• Active-area lithography and trench etch. The active pattern is printed, and a reactive-ion etch cuts through nitride, pad oxide and into the silicon to the target depth, with a deliberately sloped sidewall (around 80–85°) to ease later gap-fill.
• Liner oxidation. A thin thermal "liner" oxide is grown on the bare trench walls. This rounds the sharp top and bottom corners — sharp corners cause gate-oxide thinning and the notorious STI corner leakage hump — and repairs etch damage.
• Trench fill. The trench is filled with dielectric, historically HDP-CVD oxide and, for narrow high-aspect-ratio trenches at advanced nodes, HARP or flowable CVD oxide to avoid voids.
• Densification anneal and CMP. A high-temperature anneal densifies the oxide, then chemical mechanical planarisation grinds the overfill flat, stopping on the nitride.
• Nitride and pad strip. Hot phosphoric acid removes the nitride and the pad oxide is stripped, leaving the oxide plugs standing slightly proud of the silicon surface, ready for well implants and gate formation.

The nitride layer earns its keep twice: it masks the trench etch, and its slow polish rate makes it a near-perfect CMP stop so the final oxide height is set by the nitride, not by polish time.

Where it can go wrong

STI is unforgiving in characteristic ways. Voids trapped in the fill of narrow trenches can later fill with conductive material and short devices. Over-aggressive oxide recess after the nitride strip exposes the silicon corner, inverting it early and producing a sub-threshold "double hump" in the I–V curve. And mechanical stress from the oxide plug squeezes the adjacent silicon lattice, shifting mobility — the well-known STI stress effect, which is actually exploited as a performance knob in some technologies but must be modelled carefully.

STI in the design and modelling flow

For a layout or PD engineer, STI shows up as the active (OD/diffusion) layer and its spacing rules in the DRC deck. STI-induced stress is captured in SPICE models via length-of-diffusion (LOD) parameters, so tools such as Synopsys HSPICE/PrimeSim and Cadence Spectre read device-level STI effects straight from the extracted netlist. Process TCAD teams simulate the trench etch and fill in Synopsys Sentaurus Process, while CMP and etch recipe tuning lean on Siemens Calibre for the design-rule checking that keeps active-area density uniform enough for a flat polish. Understanding STI therefore connects the physics on the wafer to the rules you obey in the design environment.

If you want the broader process context, read our companion pieces on the oxidation process in semiconductors (the pad and liner oxides come straight from there) and on chemical mechanical planarization, the CMP step that makes STI planar. For hands-on fabrication and device-physics training, the engineers at ChipXpert's VLSI training programs cover these modules in depth.

Want to master the full front-end-of-line flow, from oxidation to STI to gate stack, with real tool exposure? Explore the Nano Fabrication track on CourseTron's course catalogue.

Frequently asked questions

Why is it called "shallow" trench isolation?

Because the trenches are only a few hundred nanometres deep, distinguishing it from deep trench isolation (several micrometres) used in power devices, image sensors and some BiCMOS processes to isolate whole wells.

What is the liner oxide for?

The thermally grown liner rounds the trench corners, repairs plasma-etch damage on the sidewalls, and provides a clean, high-quality silicon–oxide interface that reduces interface traps and corner leakage before the bulk fill goes in.

Why does STI need chemical mechanical planarization?

Trench fill deposits oxide everywhere, including a thick overburden on top of the active areas. CMP grinds that overfill back to a flat surface, stopping on the nitride, so the subsequent lithography has the planar topography it needs for tight depth of focus.

Did STI completely replace LOCOS?

For mainstream logic CMOS at 0.25 µm and below, yes. LOCOS and its variants still appear in some legacy, analog and high-voltage processes where geometries are relaxed and the simpler, cheaper flow is acceptable.