In short: The damascene process builds copper interconnects by etching trenches and vias into dielectric, overfilling them with electroplated copper, then polishing the excess away with CMP — because copper has ~40% lower resistivity than aluminum but cannot be plasma-etched cleanly, so engineers invert the flow and pattern the insulator instead of the metal.
Why copper replaced aluminum interconnect
For decades the back-end-of-line (BEOL) wiring on a chip was aluminum, patterned by depositing a blanket metal film and plasma-etching it into wires. That worked until the mid-1990s, when shrinking geometries pushed interconnect RC delay past gate delay as the dominant limiter of clock frequency. Two physical facts forced the switch to copper around the 180 nm / 130 nm nodes (IBM's 1997 CMOS 7S process being the industrial milestone):
- Resistivity. Bulk copper is ~1.68 µΩ·cm versus aluminum's ~2.65 µΩ·cm — roughly 40% lower. Lower R means less RC delay, less IR drop, and lower dynamic power on the same wire cross-section.
- Electromigration. Copper's higher activation energy for atomic diffusion (~0.9–1.1 eV vs ~0.5–0.7 eV for Al) gives it far better resistance to electromigration, so wires survive higher current densities — critical as current per wire rises each node.
Key fact: Copper has no volatile halide etch product at reasonable temperatures. You cannot "CuClx-etch" copper the way you plasma-etch aluminum into AlCl3 gas. That single chemistry problem is the entire reason damascene exists.
The damascene idea: pattern the dielectric, not the metal
The name comes from the ancient Damascus technique of inlaying metal into carved channels. In a wafer fab the logic is identical: instead of etching the metal, you etch the insulator (SiO2 or a low-k dielectric such as carbon-doped oxide / SiCOH), fill the carved openings with copper, and remove everything that sits above the surface. The dielectric becomes the mold.
Single vs. dual damascene
A single damascene flow patterns one feature per fill-and-polish cycle — a via layer, then a separate trench (line) layer, each needing its own copper plate and CMP. It is simple but doubles the number of expensive CMP steps.
Dual damascene is the workhorse of modern BEOL: it forms the via and the overlying metal line in a single copper fill. You lithographically define both the narrow via hole and the wider trench in the dielectric stack first, then plate copper once to fill both. This halves the plating/CMP count and eliminates a via-to-line interface, improving reliability.
| Attribute | Single damascene | Dual damascene |
|---|---|---|
| Features per Cu fill | One (via OR line) | Two (via + line together) |
| CMP steps per layer | Two | One |
| Via/line interface | Separate, plated twice | Monolithic, one plate |
| Typical use | Local / first metal, test | Standard production BEOL |
The two dominant dual-damascene integration schemes are via-first (etch the via hole, fill with sacrificial resist, then etch the trench) and trench-first. Via-first dominates at tight pitch because it protects the fragile low-k dielectric during the deep via etch. A middle-of-stack etch stop (e.g. SiN or SiC) defines where the trench bottom lands.
Barrier, seed, and electroplating: the fill
Copper diffuses rapidly into silicon and SiO2, poisoning transistors, so every copper feature must be hermetically wrapped in a diffusion barrier — typically a bilayer of tantalum nitride (TaN) for adhesion/blocking plus tantalum (Ta) for copper wetting, deposited by PVD or ALD at only a few nanometers thickness. On top goes a thin PVD copper seed layer that makes the sidewalls electrically continuous.
The bulk fill is electrochemical deposition (ECD / electroplating). The plating bath contains copper sulfate plus organic additives — an accelerator (SPS/bis-sulfopropyl-disulfide), a suppressor (PEG), and a leveler — that together produce superfilling: copper deposits faster at the bottom of a narrow trench than on the field, so the feature fills bottom-up and void-free. Getting these additive concentrations right is the heart of defect-free fill at sub-30 nm trench widths.
Key fact: At advanced nodes the Ta/TaN barrier can no longer scale down freely — it occupies a growing fraction of a narrow wire's cross-section and raises effective line resistance. This is why the industry is now exploring barrierless metals like cobalt, ruthenium, and molybdenum for the tightest local-interconnect layers.
Chemical-mechanical planarization (CMP)
After plating, copper covers the whole wafer — inside the trenches and as "overburden" on the field. CMP removes the overburden and the barrier, leaving copper only inside the carved features, perfectly coplanar with the dielectric. A rotating wafer is pressed against a polishing pad flooded with a chemically reactive slurry (an oxidizer plus abrasive particles). Chemistry softens the copper surface; mechanics shears it away. Copper CMP is usually a two-step recipe — a fast bulk-copper removal step followed by a selective barrier-removal step that stops on the dielectric.
CMP is also the step most prone to characteristic defects: dishing (wide copper lines polish concave), erosion (dense arrays of lines lose dielectric height), and scratching. These drive strict metal-density design rules and dummy-fill requirements that physical-design engineers encounter in tools like Cadence Innovus and Synopsys IC Compiler II, and that are verified in Siemens Calibre deck checks.
Where this fits in the design flow
Although damascene is a process-integration topic, it shapes the rules a chip designer must honor: metal-fill density windows, min/max width rules, via-array requirements for electromigration, and RC extraction models (via Synopsys StarRC or Cadence Quantus) that capture the real resistance of a barrier-lined copper wire. Understanding the physics behind these rules is what separates an engineer who merely passes DRC from one who can debug a yield or timing problem. Teams building real silicon — whether at an in-house design group or a services partner like Avecas VLSI design services — treat BEOL process awareness as core knowledge, not trivia.
Want to go from "I've heard of CMP" to building and signing off real interconnect? CourseTron's Nano Fab and Physical Design tracks walk you through BEOL integration with hands-on labs. Browse the CourseTron courses →
FAQ
Why can't we just plasma-etch copper like aluminum?
Copper halides (CuCl, CuBr) are not volatile at the moderate temperatures used in plasma etch, so etch byproducts do not leave the surface as a gas. There is no clean, anisotropic, high-throughput dry-etch chemistry for copper, which is exactly why the damascene "etch the dielectric instead" approach was invented.
What is the difference between single and dual damascene?
Single damascene forms one feature (a via or a line) per copper fill-and-CMP cycle. Dual damascene forms the via and the metal line above it in a single copper plating step, halving CMP steps and removing the via-to-line interface for better reliability.
Why does every copper wire need a barrier layer?
Copper diffuses quickly into silicon and silicon dioxide, creating deep-level traps that destroy transistor behavior. A few-nanometer TaN/Ta barrier seals the copper inside its trench and via so it cannot migrate into the active device or the dielectric.
What does CMP actually remove?
CMP removes the copper "overburden" plated on top of the wafer and the barrier layer on the field, leaving copper only inside the etched trenches and vias, coplanar with the surrounding dielectric so the next layer can be built flat on top.
For a deeper look at the polishing step itself, see our companion article on the CMP process, and for the layer that precedes metallization see low-k dielectrics. Learners who want structured, instructor-led VLSI training can also explore ChipXpert's VLSI programs.