In short: Chemical-mechanical planarization (CMP) uses a reactive slurry and a polishing pad to simultaneously etch and abrade a wafer flat so that every subsequent lithography and deposition step prints on a near-perfect plane — and dummy fill plus careful layout are the main defenses against its two signature defects, dishing and erosion.
Why a wafer needs to be made flat at all
Modern chips are built one patterned layer on top of another — sometimes 15 or more metal levels stacked above the transistors. Every deposition, etch and fill step leaves topography behind: a copper trench here, an oxide step there, a tungsten plug sticking up a few tens of nanometers. If that roughness were allowed to accumulate, the lithography scanner would be unable to focus. A 193 nm immersion stepper has a depth of focus of only around 100–150 nm, and EUV tools are even tighter at roughly 40–60 nm. Any surface variation larger than that budget means part of the exposure field is blurred, killing yield.
CMP is the only process that can flatten an entire 300 mm wafer to within a handful of nanometers across its whole surface and locally. It is the quiet workhorse that makes stacking possible — without it, the sub-7 nm logic nodes and 200+ layer 3D NAND we take for granted simply could not be manufactured.
How CMP actually works: slurry plus pad
The wafer is held face-down on a rotating carrier and pressed against a polyurethane pad on a larger rotating platen. A liquid slurry is continuously dripped onto the pad. The genius of CMP is that it is both chemical and mechanical at once:
- Chemical: oxidizers and pH-adjusters in the slurry react with the top surface, forming a soft, easily-removed layer. For copper, hydrogen peroxide oxidizes the metal; a corrosion inhibitor such as benzotriazole protects recessed regions.
- Mechanical: nanometer-scale abrasive particles — colloidal silica, alumina or ceria, typically 20–100 nm — carried in the slurry, together with the pad asperities, shear that soft layer away only where the pad touches the high spots.
Because the reacted film is removed fastest where pressure is highest (the protrusions), high regions polish down far faster than recesses. The net effect is global and local planarization. Typical process knobs are downforce (around 2–5 psi), platen speed (50–120 rpm) and slurry flow (100–250 ml/min). Pad conditioning — a diamond disk that re-roughens the glazed pad between wafers — is critical and often the hidden cause of drift.
The two villains: dishing and erosion
CMP's great weakness is that the pad is not infinitely stiff. It deflects into wide, soft features, which creates two closely-related defects you will be asked about in any backend or DFM interview:
Dishing is the recessing of a single wide feature — a large copper pad or bond pad — below the surrounding dielectric. A 100 µm-wide copper line can dish by 30–80 nm because the pad bows into it and keeps polishing the soft metal after the field is already clear.
Erosion is thinning across a dense array of fine features — e.g. a region packed with narrow metal lines and thin dielectric spaces. The combined surface is mostly soft metal, so the whole band is removed faster than a sparse area, leaving a shallow valley tens of nanometers deep.
Both increase line resistance (less copper cross-section), hurt RC timing, and can leave residual metal shorts if under-polished. They are strongly pattern-density dependent — which is exactly why layout, not just the tool, controls the outcome.
| Defect | Where it appears | Primary cause | Typical magnitude |
|---|---|---|---|
| Dishing | Isolated wide metal | Pad deflection into the feature | 30–80 nm |
| Erosion | Dense fine-line arrays | High local metal density | 20–50 nm |
| Residue / under-polish | Low-density regions | Insufficient removal | metal shorts |
Dummy fill: the layout cure
Because CMP uniformity depends on keeping pattern density uniform, design teams add dummy fill (also called tiling or metal fill) — electrically inert metal and oxide shapes dropped into empty regions so that every window of the chip has a similar metal density, usually targeted inside a 20–80% band. Foundry rules specify a density window and gradient limit per layer; the sign-off deck checks it.
This is handled automatically in physical-design and sign-off tools. Cadence Innovus and Synopsys IC Compiler II insert metal fill during routing, while Siemens Calibre runs the density and CMP-aware checks (Calibre YieldEnhancer SmartFill and Calibre CMPAnalyzer) that predict the post-polish surface and flag hotspots before tapeout. A good flow iterates: route, fill, run a CMP model, and re-fill the worst regions. For a practical walk-through of how fill ties into the wider backend flow, our course and the design-services team at Avecas VLSI design services cover real tapeout decks.
Where CMP sits in the process flow
CMP appears in two main places. In the front end, STI (shallow-trench isolation) CMP planarizes the oxide that isolates transistors, and ILD CMP flattens the dielectric before contacts. In the back end, every copper interconnect level uses CMP as the final step of the damascene process: etch a trench in dielectric, barrier/seed, electroplate copper to overfill, then CMP away the overburden so only the inlaid wiring remains. Tungsten-plug CMP and, more recently, cobalt and hybrid-bonding CMP for 3D stacking follow the same principles. It pairs tightly with the deposition steps that precede it — see our companion piece on CVD, PVD and ALD deposition and on copper damascene interconnect.
Want to go from "I can define dishing" to confidently debugging a CMP density hotspot in a real sign-off deck? Our Nano Fab & Backend track builds exactly this intuition — explore the CourseTron courses. Hands-on tool training is also run with ChipXpert's VLSI training.
Metrology and endpoint
You cannot planarize what you cannot measure. Removal is controlled with endpoint detection — optical reflectance or motor-current (friction) signals that spike when a layer clears — plus post-CMP measurement by profilometry, reflectometry and, for defects, automated optical inspection. A 50 nm over-polish of copper can shift a timing-critical net by enough to miss setup; CMP recipes therefore trade removal rate (often 300–800 nm/min) against uniformity and defectivity.
FAQ
Is CMP purely mechanical polishing?
No. If it were only mechanical you would scratch and damage the surface; if it were only chemical you would etch isotropically and keep the topography. The two acting together — chemistry softening the surface, abrasion removing it preferentially at high points — is what gives both planarity and low defectivity.
Why do we add dummy metal that carries no signal?
To equalize pattern density so CMP removes material uniformly. Empty regions polish differently from dense ones, causing dishing and erosion. Inert fill shapes keep local density inside the foundry's window, flattening the post-polish surface. They are tied to nothing (or to ground/shield) and are purely for manufacturability.
What is the difference between dishing and erosion?
Dishing is recessing of one wide, isolated feature below its surroundings. Erosion is overall thinning across a dense array of fine features. Dishing is a single-feature problem driven by pad bending; erosion is a density problem driven by a whole region being softer than average.
Which tools model CMP before tapeout?
Siemens Calibre CMPAnalyzer and YieldEnhancer predict the polished surface and insert smart fill; Synopsys IC Compiler II and Cadence Innovus perform density-driven fill during implementation. The flow iterates fill and CMP modeling until density gradients meet sign-off rules.