In short: Autorouters are excellent at clearing the bulk of low-speed, forgiving nets quickly, but timing-, impedance- and return-path-critical nets must be routed by hand (or with guided interactive tools), because only the designer knows the physics the router is not told about.
Where autorouting genuinely helps
Autorouting has a bad reputation among experienced layout engineers, but the reputation is only half deserved. A router is a search algorithm: given pads, obstacles, layers and clearance rules, it finds a conflict-free path for every connection. That is exactly what you want for a 200-net board of GPIO, LED drivers, reset lines, I2C buses at 100 kHz and slow sensor inputs. None of these nets care if a trace is 38 mm or 61 mm long, and a router will finish them in seconds instead of the hours a human would spend.
Autorouting also earns its keep in three other situations. First, early feasibility: running a router on a rough placement tells you within minutes whether a 4-layer stackup can possibly fit, or whether you need six. Second, dense but uniform structures such as LED matrices, keypad scans and memory-style address fans where every net has similar constraints. Third, rework at scale, where a connector pinout changes and dozens of simple nets need re-pathing.
Key fact: A typical microcontroller board has 70-85% of its nets with no electrical constraint beyond clearance and current. The remaining 15-30% are the nets that decide whether the board works.
Why critical nets are routed by hand
A conventional autorouter optimises completion and via count. It does not understand that a net is a transmission line. The nets it mishandles fall into predictable families.
- Controlled-impedance nets. A 50 Ω single-ended or 90 Ω USB pair depends on trace width, dielectric height and a continuous reference plane. A router that hops layers freely changes the reference plane, and every layer change without a nearby ground via is an impedance and return-path discontinuity. See our guide to signal integrity in PCB for the underlying theory.
- Length-matched groups. Signal propagation in FR-4 microstrip is roughly 6 ps/mm (about 150 ps per inch). A DDR byte lane that must match within 25 mil (0.64 mm) has a timing budget of only about 4 ps of skew from routing, which a router cannot hit without explicit tuning geometry.
- Differential pairs. Both legs must stay coupled, symmetrical and equal in length, with the same via transitions. Detail is covered in differential pair routing in PCB.
- Noisy and sensitive nets. Switching-regulator hot loops, crystal traces and analog front ends need short, compact, deliberately placed copper. Automated routing spreads parallel runs without regard to crosstalk in PCB, which grows with parallel run length and shrinks roughly with the square of spacing-to-height ratio.
- Power delivery. Wide planes and pour shapes for current paths and low-inductance decoupling loops are a placement-plus-routing problem; see power integrity in PCB.
A concrete example: why skew matters
Take a 1.6 GHz DDR3 address clock with a 625 ps period. If the data strobe and clock paths differ by 12 mm on FR-4, that is roughly 72 ps of extra delay, over 11% of the period, before setup and hold margins are even counted. An autorouter that treats these as ordinary connections will happily produce that mismatch. A designer instead routes the group with serpentine tuning, keeps gaps at three times trace width or more to avoid self-coupling, and then verifies against the memory controller's timing guide.
How KiCad implements interactive routing
KiCad's PNS (push-and-shove) router, started with the X key on a pad or track, is the human-in-the-loop alternative. It offers three collision behaviours: highlight collisions (draw through and flag violations), walk around (the trace bends around obstacles) and shove (existing tracks and vias are pushed aside while keeping clearance). Design rules defined in Board Setup, including net classes, width and clearance per class, differential-pair gap and via sizes, constrain what the router may do, so a USB pair snaps to 90 Ω geometry as you route it. Separate tuning tools lengthen a single track or a differential pair with meanders to hit a target length. KiCad ships no built-in full autorouter. Instead it exports a Specctra DSN file that external tools such as the open-source Freerouting can process, returning a SES file you import back into the board.
How Altium Designer implements interactive routing
Altium's Interactive Routing exposes conflict resolution modes: Ignore Obstacles, Walkaround Obstacles, Push Obstacles, Hug and Push, and Stop At First Obstacle. Its engine adds "ActiveRoute", which routes selected connections against guidance you set, such as layer preferences and routing paths, and the Situs autorouter handles the bulk. Length and delay constraints are expressed through xSignals, which can span a pull-up resistor or series termination so that the whole path, not just one net, is matched. Cadence Allegro offers comparable auto-interactive delay tuning, and Siemens Xpedition uses a sketch-routing approach where you draw a rough intent and the tool completes the geometry. In every case the pattern is the same: the human supplies intent, the tool supplies precision.
| Aspect | Autorouter | Interactive / manual |
|---|---|---|
| Speed on simple nets | Seconds | Minutes to hours |
| Length matching | Weak without constraints | Precise, with tuning tools |
| Return-path awareness | None by default | Designer-controlled |
| Escape from BGAs | Often wasteful on vias | Planned pattern |
| Repeatability | High | Depends on the engineer |
The animation: why a longer path arrives late
Where each approach fails: BGAs and manufacturability
Fine-pitch BGAs expose another autorouter weakness. Escape routing from a 0.8 mm-pitch BGA requires a planned via-in-pad or dog-bone pattern, layer assignment by ball ring and consistent channel usage. See BGA routing techniques for the standard patterns. Automated results can burn extra layers and use more via types than a planned fan-out would, raising fabrication cost. Check the result against DFM for PCB rules such as minimum annular ring, acid traps and copper balance. Layer count itself is a trade-off discussed in single vs multilayer PCB.
Key fact: An unplanned extra signal layer typically adds 15-30% to bare-board cost, so a 20-minute manual escape plan often pays for itself on the first production order.
A practical rule of thumb for interviews
Hiring managers asking this question want a decision framework, not a slogan. Classify nets first, then pick the tool. Route power, clocks, high-speed buses and analog by hand under rules. Constrain, then autoroute, the leftover low-speed nets. Review the result for stubs, acute angles, plane splits and return-path breaks. Teams building such flows professionally, including those at Avecas design services, usually script net-class assignment so the split between hand and auto routing is reproducible. If you also want hands-on training in physical design flows, our sister brand ChipXpert covers the chip side of the same discipline.
Key fact: Autorouters satisfy the rules you gave them; they cannot satisfy rules you forgot to write. Hand-routing is largely the act of writing those missing rules in copper.
Ready to practise real layout flows? Explore the hands-on PCB design modules in our CourseTron courses and route your first controlled-impedance board.
Frequently asked questions
Should I ever fully autoroute a board?
Only for simple, low-speed boards with no length, impedance or noise constraints, or for a quick feasibility study. Production boards with any high-speed content should be hybrid routed.
Does KiCad have an autorouter?
Not built in. KiCad exports Specctra DSN so external routers such as Freerouting can route the board, and you import the SES result.
What is ActiveRoute in Altium?
It is a guided routing feature that completes selected connections following your layer and path preferences, giving a middle path between full manual and full automatic routing.
How much length mismatch is acceptable?
It depends on the interface, derived from the timing budget. For a 6 ps/mm trace, a 25 mil (0.64 mm) tolerance equals about 4 ps; always follow the controller and memory vendors' layout guides.