In short: Surface-mount devices (SMDs) are components soldered directly onto copper pads instead of through holes, and you choose between packages such as 0402, 0603, 0805, SOIC, QFN and BGA by balancing pin count, power dissipation, board density, assembly yield and rework cost.
What is a surface-mount component?
A surface-mount device sits on top of the board and is soldered to flat copper pads. There are no drilled holes for leads, so both sides of the board can carry parts, and the component body is far smaller than a through-hole equivalent. A 1 kΩ resistor in a leaded axial package is about 6 mm long; the same resistor in an 0402 chip package is 1.0 mm long. That size gap is the reason phones, wearables and SSDs exist. If you are new to the board itself, start with what a PCB is, then come back here.
Surface mounting also changes manufacturing. Through-hole parts need wave soldering or manual work; SMDs are placed by a pick-and-place machine at tens of thousands of parts per hour, then all joints form at once inside a reflow oven. Fewer drilled holes also means shorter signal paths, lower lead inductance and better high-frequency behaviour.
Passive chip sizes: 0402, 0603 and 0805
Resistors, capacitors and inductors come in rectangular chip packages named by a four-digit code. In the imperial system the code is length and width in hundredths of an inch, so 0603 means 0.06 in by 0.03 in. The metric code is in tenths of a millimetre, so the same part is "1608". Mixing the two systems is a classic way to order the wrong parts: imperial 0402 (1.0 x 0.5 mm) is not metric 0402 (which is imperial 01005, only 0.4 x 0.2 mm).
Key fact: Power rating scales with package area. A 0402 resistor is typically rated about 0.063 W, a 0603 about 0.1 W and an 0805 about 0.125 W at 70 °C, and the rating must be derated as ambient temperature rises.
For multilayer ceramic capacitors there is a second reason to go larger: the DC-bias effect. A 10 µF X5R capacitor in 0402 can lose more than half its capacitance at 5 V bias, while the same value in 0805 loses much less because the dielectric is thicker. Designers who skip this check discover noisy rails during bring-up. In practice, 0402 is a good default for dense digital boards, 0603 for mixed-signal and prototype work, and 0805 where current, voltage or hand assembly matter.
Packages for integrated circuits
ICs use three broad families, and each solves a different problem.
- SOIC (Small Outline IC): gull-wing leads on two sides, 1.27 mm pitch, 3.9 mm body width for the common SOIC-8. The leads are visible, so you can inspect and touch up joints with an iron. It suits op-amps, regulators and logic.
- QFN (Quad Flat No-lead): pads sit under the body edge with no protruding leads, pitch usually 0.4 to 0.65 mm, and a large exposed thermal pad in the centre. Lead inductance is tiny and heat flows straight into the board, which is why power ICs and RF parts favour it.
- BGA (Ball Grid Array): an array of solder balls under the package, pitch from 1.0 mm down to 0.4 mm. A 17 x 17 mm BGA can carry 400 or more connections, impossible with perimeter leads. FPGAs, processors and DDR memory live here.
How assembly differs
All three families use the same process: print solder paste through a stencil, place parts, reflow. What changes is the tolerance. Stencils are commonly 100 to 125 µm thick, and the area ratio (aperture area divided by aperture wall area) should stay above roughly 0.66 so paste releases cleanly. Fine-pitch QFN and BGA apertures push that limit, which is why some boards use a 100 µm stencil with nano-coating.
Reflow follows a profile: preheat, soak, a short time above liquidus, then cooling. For lead-free SAC305 solder the liquidus is 217 °C and peak temperature is typically 240 to 250 °C, with 40 to 90 seconds above liquidus. The animation below shows a part moving through that profile.
Key fact: Small chips heat faster than large neighbours. If one pad of an 0402 wets before the other, surface tension pulls the part upright, a defect called tombstoning. Symmetric pads and traces, and equal copper on both ends, prevent it.
Common defects and how to avoid them
- Tombstoning and skew on small passives: balance pad copper and avoid one pad tied to a large plane without a thermal spoke. See thermal reliefs and teardrops.
- Bridging on fine-pitch SOIC and QFN: use solder-mask dams between pads and keep paste volume controlled.
- Voiding under the QFN thermal pad: split the pad paste into a window-pane pattern so flux gas can escape, and aim for under 25 percent voiding.
- Head-in-pillow on BGAs: caused by package warpage during reflow; a nitrogen atmosphere and a well-matched profile help.
Inspection also scales with package type. Automated optical inspection (AOI) catches most chip and SOIC faults. QFN side wettable flanks help AOI, but BGA balls need 2D or 3D X-ray. Rework is the real cost: a bad SOIC can be fixed with a hot-air tool in minutes, while a BGA needs a rework station, reballing and a fresh profile, and it can only be reworked a limited number of times.
Routing and layout consequences
Package choice drives your layout rules. Land patterns should follow IPC-7351, which Cadence Allegro, OrCAD, Siemens Xpedition and PADS libraries implement in three density levels (most, nominal, least). A 0.5 mm pitch QFN usually allows one trace between pads only at 3 to 4 mil, whereas a 1.0 mm BGA can use through-hole vias between balls, while 0.8 mm and tighter pitches typically need microvias; compare the options in via types in PCB. For escaping dense ball arrays, read the dedicated guide on BGA routing techniques.
How to choose: a practical checklist
| Need | Typical pick | Reason |
|---|---|---|
| Dense phone or wearable board | 0402, QFN, fine-pitch BGA | Smallest area per function |
| Prototype or hand assembly | 0603, 0805, SOIC | Easy to see and solder |
| Power dissipation above 0.5 W in the IC | QFN with thermal pad, power SOIC | Direct path to copper |
| Hundreds of I/O | BGA | Area array beats perimeter leads |
| Low volume, low budget | Avoid BGA below 0.8 mm pitch | Needs HDI and X-ray inspection |
Ask four questions in order. How many pins? How much heat? Who assembles it and how will it be inspected? What does the fabricator's capability sheet allow, since 3 mil traces and microvias raise the price? Interviewers often ask exactly this: "why 0402 and not 0201, or QFN and not SOIC?" A strong answer names pitch, thermal path, inspection and yield, not just size. If your team needs design help, Avecas offers board design services, and ChipXpert runs hands-on training that pairs well with these ideas.
Want to design real boards with confident package choices? Explore the hands-on PCB tracks in our CourseTron courses and build your first SMD layout today.
FAQ
What is the difference between 0402 and 0603?
0402 is 1.0 x 0.5 mm and 0603 is 1.6 x 0.8 mm (imperial codes). 0402 saves area but has lower power rating and is harder to hand-solder and inspect.
Is QFN or BGA easier to assemble?
QFN is easier. Its edge pads are partly visible and it can be reworked with hot air, while BGA balls are hidden and need X-ray inspection and a rework station.
Why do some SMD parts tombstone?
One end of a small chip melts and wets before the other, so surface tension lifts the part upright. Balanced pad size, copper and paste volume solve most cases.
Which package handles heat best?
QFN with a soldered exposed pad, or a BGA with thermal balls, conducts heat best into the board. Plain SOIC leads are weaker thermal paths.