In short: BGA routing is the craft of pulling hundreds of ball signals out from under a package by fanning each ball to a via, then escaping those vias into routable channels — and whether you win or lose is decided by your ball pitch, via geometry, and how many signals you can push through each layer.
A modern SoC, FPGA, or memory package can hide 500 to 2,000 balls under a 25 mm×25 mm footprint. None of those signals are usefully accessible on the surface — they sit on a grid with nothing but solder mask between them. BGA routing is the set of techniques that gets every one of those nets out to the rest of the board without violating your fabricator's design rules. Get it wrong and you add layers (cost), fail impedance targets (signal integrity), or simply can't route the part at all.
Why BGA pitch dictates everything
The single most important number in a BGA design is the ball pitch — the center-to-center spacing of adjacent balls. A 1.0 mm pitch part is forgiving; a 0.4 mm pitch part (common on mobile SoCs and HBM stacks) is brutal. The pitch sets how much copper you have between two neighboring vias, which in turn decides whether you can route a trace through that gap at all.
The usable channel between two adjacent dog-bone vias is roughly: pitch − via pad diameter − 2×(trace-to-copper clearance). On a 0.8 mm pitch part with an 18 mil via pad and 4 mil clearance, you have about 0.8 mm − 0.46 mm − 0.20 mm ≈ 0.14 mm (5.5 mil) of channel — enough for one 4 mil trace. Drop to 0.5 mm pitch and that channel vanishes, which is exactly why fine-pitch parts force via-in-pad and HDI stackups.
Rule of thumb: with standard (non-HDI) vias you can escape at most the outer 2–3 ring rows per signal layer through the channels between balls. Everything deeper needs either more layers or microvias.
Fanout: giving every ball a landing
Fanout is the first step. Each BGA pad is connected to a via (or microvia) that drops the signal to an internal or opposite layer where there is room to route. Tools like Cadence Allegro, Siemens Xpedition, and Altium Designer all ship automated BGA fanout commands that place vias on a programmable pattern — but understanding the geometry by hand is what lets you fix the 5% the autorouter can't.
Dog-bone vias vs. via-in-pad
There are two dominant fanout styles.
- Dog-bone (via beside pad): a short neck connects the ball pad to a via placed in the ball-to-ball gap. Cheap and manufacturable with standard through vias, but it consumes channel space and only works down to about 0.65–0.8 mm pitch.
- Via-in-pad (VIP): the via is drilled directly inside the ball pad. This reclaims the channel entirely and is mandatory below ~0.5 mm pitch. The catch: an open via under solder wicks paste away and causes voids, so VIP must be filled and plated over — a non-conductive or conductive epoxy fill, then copper plating and planarization. That is an extra fab process (type VII HDI) and adds cost.
| Technique | Typical pitch | Channel cost | Fab complexity |
|---|---|---|---|
| Dog-bone, through via | ≥ 0.8 mm | High (eats channel) | Low |
| Dog-bone, microvia | 0.5–0.8 mm | Medium | Medium (HDI) |
| Via-in-pad (filled/plated) | ≤ 0.5 mm | None | High |
If you want the full tradeoff across blind, buried, and stacked structures, our companion article on via types in PCB design breaks down the plating and aspect-ratio limits in detail.
Escape routing: getting out of the array
Once every ball has a via, escape routing threads those vias out past the package edge into open board space. The classic strategy is layer-by-layer ring peeling: route the outermost ball ring on the top layer, the next rings on successive internal layers, and the innermost power/ground rings on dedicated planes where they only need a via drop, not a trace.
A well-known heuristic: a BGA needs roughly N/2 − 1 signal layers to escape a fully-populated N×N signal array through standard channels. A 16×16 all-signal array therefore wants ~7 signal layers — which is why high-pin FPGAs live on 10–16 layer boards.
Differential pairs complicate this: both nets of a pair must escape through the same channel to stay length- and skew-matched, so you often reserve two-wide channels and route pairs on the same layer from entry to connector. Siemens HyperLynx and Cadence Sigrity are the go-to tools for verifying that your escape geometry still hits the 85 Ω or 100 Ω differential impedance target after the via transition.
A signal escaping in motion
Practical checklist before you route
- Pull real design rules from your fab (min trace/space, min annular ring, min drilled via) before placing a single via — not after.
- Assign power and ground balls to planes early; they don't need channels and free up routing for signals.
- Keep differential pairs on one layer, same channel, from ball to exit.
- For VIP parts, confirm the fab offers filled-and-plated vias and budget for it.
- Run post-route SI/PI extraction — a geometrically legal escape can still fail impedance.
If your layout outgrows a standard stackup, consider whether an HDI approach pays for itself, or whether a board-level partition into multiple modules is cheaper. Teams at Avecas VLSI design services regularly make exactly this layer-count-versus-cost call on high-pin-count SoC boards.
Want to route real FPGA and SoC packages hands-on in Allegro and Xpedition? The CourseTron PCB & High-Speed Design track walks you from fanout to signal-integrity sign-off on production boards.
Frequently asked questions
When do I have to switch from dog-bone to via-in-pad?
Generally at or below 0.5 mm ball pitch. Around 0.65–0.8 mm you can still dog-bone with microvias; below that the channel simply disappears and VIP becomes the only way to reclaim routing space.
Why does via-in-pad need to be filled and plated over?
An open via drilled into a solder pad wicks solder paste down the barrel during reflow, starving the joint and creating voids or a tombstoned part. Filling the via with epoxy and plating a flat copper cap restores a solid, solderable surface.
How many layers will my BGA need?
Estimate with the ring-peeling heuristic: a fully-signal N×N array needs roughly N/2−1 signal layers to escape through standard channels. Power/ground balls route on planes and reduce the count. High-pin FPGAs typically land on 10–16 layer stackups.
Can the autorouter do BGA fanout for me?
Fanout patterns yes — Allegro, Xpedition, and Altium all automate via placement. Full escape and length-matched differential routing usually still need manual intervention for the densest inner rings and for impedance-critical nets.