In short: A switching supply layout is good when the pulsed input loop is tiny, the switch node is small, the feedback path is quiet and kept away from it, and ground returns are routed so that switching current never flows through the reference the controller measures.
A buck converter schematic that works in simulation can still fail EMI testing, ring at 40 V on a 12 V rail, or run 30 degrees hotter than predicted. The schematic is identical in every case. What differs is the copper. Layout decides parasitic inductance, and in a converter that switches several amps in a few nanoseconds, parasitic inductance is the dominant circuit element.
Why layout matters: di/dt and the hot loop
In a synchronous buck, the current through the input capacitor, the high-side FET and the low-side FET is not smooth. It is a trapezoidal pulse that jumps from zero to the full load current and back every cycle. That path is the hot loop (also called the commutation loop): input capacitor, high-side switch, low-side switch, and back to the capacitor ground.
The voltage spike across a parasitic inductance is V = L × di/dt. Take a 10 A step in 5 ns, which is 2 A/ns. A hot loop of 10 nH (roughly a 2 cm long, 1 cm wide loop on a 4-layer board with a distant return) produces 20 V of ringing. Shrink the loop to 2 nH and the spike falls to 4 V. The energy stored in that loop inductance, ½LI², also rings with the FET output capacitance, creating the high-frequency noise that appears at 100 to 300 MHz on a spectrum analyser.
Key fact: loop inductance scales roughly with enclosed area. Halving the loop area roughly halves the spike and the radiated field.
Placing the hot loop first
Place components in loop order, not schematic order. Start with the two FETs (or the integrated converter), then the input ceramic capacitors, then everything else. Use these rules in Altium, Cadence Allegro, Siemens Xpedition or KiCad alike:
- Put the smallest, fastest ceramic (for example 100 nF to 1 µF in 0402 or 0603, X7R) closest to the FET pins. Bulk capacitors can sit farther away.
- Keep the loop on one layer where possible. Where a via is unavoidable, use several, because each via adds around 0.5 to 1 nH.
- Run the return path on layer 2 directly under the loop, with a solid unbroken plane. The image current in the plane cancels most of the loop field; this is why a gap or slot there is so damaging, as discussed in ground and power plane splits.
- Remember that DC bias derates ceramics. A 10 µF 25 V 0805 may offer only 3 µF at 12 V, so check the vendor curve.
Key fact: a 1 µF capacitor with 1 nH of mounting inductance has a self-resonance near 5 MHz. Past that it behaves as an inductor, so placement matters more than capacitance value.
Switch-node copper: small but not too small
The switch node (SW) swings between ground and VIN with edges of 1 to 5 V/ns. Any copper attached to it is an antenna and also couples capacitively to nearby traces. The competing need is current: SW carries the full inductor current and the FETs dump heat through it.
The practical compromise is to make SW a short, wide polygon just big enough to connect the FET pins and the inductor, then stop. Do not pour SW to help cooling; use ground or VIN copper for that. Never route sensitive signals on the layer directly beneath SW, and keep the layer under it a solid ground plane so it acts as a shield rather than a coupling path. A good rule of thumb is a SW area below roughly 1 cm² for a 5 to 10 A stage.
If edge ringing is still a problem, add a bootstrap resistor of 2 to 5 Ω in series with the bootstrap capacitor to slow the high-side turn-on, or place a small RC snubber from SW to ground within millimetres of the low-side FET.
Feedback routing and grounding
The feedback divider senses the output and controls the loop. Pick up noise here and the converter shows jitter or sub-harmonic oscillation. Follow these steps:
- Take the sense point at the output capacitor, not at the inductor. Run it as a thin trace (0.15 to 0.2 mm) away from the inductor and SW.
- Place the divider resistors next to the FB pin, with the lower resistor grounded to the controller's analogue ground pin, and keep the high-impedance FB node short.
- Shield the FB trace with ground on both sides and a plane below. Keep it over 5 mm from the inductor, since a gapped magnetic field couples easily.
- Use a single-point tie between power ground (PGND) and analogue ground (AGND), ideally under the controller's exposed pad.
Seeing the current path
The animation below traces one switching cycle. Charge flows from the input capacitor through the high-side FET during the on-time. When the controller turns it off, the inductor forces current through the low-side FET. The pulse repeats every period, and a tight loop keeps the stored energy in the green path small.
Thermal copper and vias
A converter running at 95% efficiency still dissipates 5% of its output power. At 60 W out, that is about 3 W in a package smaller than a fingernail. The heat leaves mainly through the exposed pad and the copper around it. Use a 3 x 3 grid of 0.3 mm plated vias (1.0 to 1.2 mm pitch) in the pad to carry heat to inner and bottom ground layers, and use 2 oz copper where the board allows. Fill or cap vias if solder wicking is a risk. The effects on reflow and the balance of copper weights are covered in PCB thermal management, and heat-spreading tradeoffs in copper balancing. For connections to large planes, see thermal reliefs and teardrops; power pads should use solid or generous spokes, not thin ones, to avoid adding thermal resistance. Power rails then need the broader strategy in power integrity in PCB.
| Layout item | Target | Why |
|---|---|---|
| Hot loop inductance | Below 2 to 3 nH | Limits spike and EMI |
| Switch-node area | Under about 1 cm² | Less capacitive coupling |
| FB trace distance from inductor | Over 5 mm | Avoids field pickup |
| Exposed-pad vias | 9 to 16 at 0.3 mm | Lower thermal resistance |
| Return plane under loop | Unbroken | Image current cancels field |
Verifying the result
Review the board before release. In Cadence Allegro or Siemens HyperLynx, run a PDN or loop-inductance extraction on the input loop. Then measure on the bench with a 20 MHz bandwidth-limited probe and the ground spring tip, not the long lead, since the lead would add its own inductance and create fake ringing. Compare SW overshoot to the FET rated VDS with at least 20% margin. Teams that need an independent review can use design services from Avecas, and learners who want guided practice can explore ChipXpert training. Structured courses are listed on the CourseTron courses page.
Want to practise layout on real converter boards? Join the CourseTron PCB design course and build, review and measure a working buck converter step by step.
Frequently asked questions
What is the most important rule in SMPS layout?
Minimise the hot loop area formed by the input capacitor and the two switches, and give it a solid return plane directly beneath.
Should the switch node be a big copper pour?
No. Keep it only large enough for the current and the inductor connection. Large SW copper radiates and couples noise; use ground or input copper for cooling instead.
Where should I connect AGND and PGND?
At a single point, usually under the controller's exposed pad, so switching current never flows through the analogue reference.
How many thermal vias does a power IC need?
Typically 9 to 16 vias of 0.3 mm in the exposed pad, with the exact count set by the datasheet and package power dissipation.