In short: Power integrity on a PCB is the art of keeping the power distribution network (PDN) impedance below a frequency-dependent target impedance from DC up into the hundreds of MHz, so that switching current demand never turns into supply-rail ripple that corrupts your logic.
Every digital chip on your board is, electrically, a current pump that slams charge in and out of its supply pins each clock edge. The power distribution network — the regulator, the planes, the vias, and above all the decoupling capacitors — has to deliver that charge without the rail sagging or ringing. When engineers say a design has "good power integrity," they mean the impedance that a switching load sees looking back into the PDN stays flat and low across the whole frequency band of interest. This article walks through target impedance, PDN impedance versus frequency, and how decoupling is really a problem of stitching capacitors together across decades of frequency.
Why ripple is really an impedance problem
Ohm's law in the frequency domain tells the whole story: ripple voltage equals transient current times PDN impedance, ΔV = ΔI × Z(f). If a 1.0 V core rail draws a 5 A transient and you allow 5% ripple (50 mV), then the PDN must present no more than 10 mΩ to that current at every frequency where the current has spectral content. Because digital current transients are sharp-edged, that spectral content reaches from DC up to well past 100 MHz. So power integrity is not "add some caps" — it is a broadband impedance-shaping exercise.
Target impedance formula: Ztarget = (Vrail × ripple%) ÷ Itransient. A 0.9 V FPGA rail with a 20 A worst-case step and a 3% budget needs Ztarget ≈ 1.35 mΩ — brutally low, and the single hardest number to hit in modern designs.
The PDN impedance curve, from DC to GHz
Different parts of the PDN dominate in different bands. At DC the regulator's output resistance and copper IR drop set the floor. From roughly DC to a few hundred kHz the voltage regulator module (VRM) and its control loop hold the rail. Above the VRM's reach, bulk electrolytic or large ceramic caps take over into the low MHz. Mid-frequency (1–100 MHz) is the realm of many small MLCCs. Above ~100 MHz, the power/ground plane pair and the chip's own on-die capacitance are all that respond — board capacitors are already inductive by then.
Anti-resonance: the villain between capacitor banks
The counterintuitive hazard is that where two capacitor types hand off, the inductance of the larger cap resonates with the capacitance of the smaller one, forming a parallel LC tank that raises impedance to a sharp peak — anti-resonance. A board can have excellent caps and still fail power integrity because a peak pokes above the target line at, say, 40 MHz, exactly where the DDR controller switches. The fix is not more of one value but a graded spread of values and, critically, controlling mounting inductance.
Mounting inductance dominates. A 0402 MLCC's own ESL is ~0.5 nH, but a sloppy footprint with a long trace to a distant via can add 2–3 nH. At 50 MHz, 2 nH is ≈0.63 Ω — hundreds of times your target. This is why decoupling capacitor placement and via-in-pad matter more than raw capacitance.
Building the capacitor stack across frequency
Think of decoupling as a relay team. Each capacitor is only useful near its self-resonant frequency (SRF), where its impedance dips to its ESR. Below SRF it looks capacitive; above SRF it looks inductive. You choose values so their SRF dips overlap and tile the band.
| Band | Element | Typical value | What it supplies |
|---|---|---|---|
| DC–100 kHz | VRM + bulk | 100–470 µF | steady load, slow steps |
| 100 kHz–2 MHz | bulk ceramic / tantalum | 10–47 µF | block/burst transients |
| 2–50 MHz | MLCC 0402/0201 | 0.1–1 µF | per-pin switching |
| 50 MHz–GHz | plane pair + on-die | pF range | edge-rate current |
Vendors like Cadence (Sigrity/Clarity), Siemens (HyperLynx PI/PowerSI) and Ansys (SIwave) let you sweep the PDN impedance from a few kHz to 1 GHz and overlay the target line, then auto-suggest a cap mix that flattens anti-resonance. For teams that build their own boards, our design partners at Avecas VLSI design services run exactly these PDN sign-off sweeps before fab-out.
A worked placement example
Suppose a 1.2 V DDR4 controller with a 12 A transient and a 4% budget: Ztarget = 1.2 × 0.04 / 12 = 4 mΩ. No single cap gets you there. You might place eight 0.1 µF 0201s directly under the BGA (SRF ~50 MHz), sixteen 1 µF 0402s in the next ring, four 22 µF bulk ceramics at the rail entry, and rely on a tight 3 mil power/ground dielectric to carry the top decade. Parallel enough small caps and their ESRs divide down to the mΩ floor. The plane spacing is free capacitance — halving the dielectric thickness doubles plane capacitance and pushes the high-frequency wall outward.
Want the hands-on flow — reading an impedance sweep, fixing an anti-resonance, and laying out the cap rings? Our CourseTron PCB courses cover it with real board files, and the companion piece on PDN plane and stack-up design digs into the dielectric side.
Master PDN design end-to-end — enroll in CourseTron's Signal & Power Integrity track and work through live board simulations with industry tools.
Frequently asked questions
What is target impedance in a PDN?
It is the maximum impedance the power distribution network may present so that the worst-case transient current produces no more than the allowed ripple. It equals rail voltage times the ripple fraction divided by the transient current, and it must be met across the whole frequency band the load excites.
Why do I need capacitors of several different values?
Each capacitor only has low impedance near its self-resonant frequency. A spread of values tiles the frequency axis so that as one cap becomes inductive, the next value's resonance takes over, keeping the composite impedance flat and below target.
What causes anti-resonance peaks?
When the inductance of a larger capacitor resonates with the capacitance of a smaller one in parallel, the two form an LC tank that spikes impedance between their bands. Grading cap values and minimizing mounting inductance suppresses these peaks.
Does capacitor placement really matter that much?
Yes. Mounting and via inductance usually dominate a small MLCC's effectiveness above a few MHz. A capacitor placed far from the pin with long traces can add nanohenries that swamp its value, so placement and via-in-pad routing are decisive.