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In short: Good decoupling capacitor placement puts the smallest bypass caps as close as physically possible to each power pin, keeps the loop to the planes tiny, and uses a spread of values so the power distribution network stays low-impedance across frequency. Proximity and loop inductance matter far more than the printed capacitance value.
What is decoupling capacitor placement?
Decoupling capacitor placement is the practice of positioning bypass (decoupling) capacitors on a PCB so they can supply the fast, transient current an IC demands without letting the supply voltage sag or ring. Every time a digital chip switches, millions of transistors pull charge from the power rail in nanoseconds. The voltage regulator is far too slow and too far away to answer that demand. A nearby capacitor acts as a tiny local reservoir, delivering the burst of charge and then recharging slowly between events.
The job is part of designing the Power Distribution Network (PDN) — the whole path of planes, vias, and capacitors that carries power from the regulator to the die. A capacitor only decouples well if the inductance between it and the chip is small, and that is governed almost entirely by where you put it and how you route it, not by the value stamped on the part.
Key fact: A 100 nF capacitor placed 10 mm from a power pin can be electrically useless above ~50 MHz because the loop inductance of the traces and vias dominates. The same part placed under the pin, on a short via to the plane, stays effective far higher in frequency.
Why the Power Distribution Network needs decoupling
Think of the PDN as a target impedance problem. The chip tolerates only a small ripple on its supply — say 5 % of 1.0 V = 50 mV. If it draws transient current ΔI, the PDN impedance must satisfy Z ≤ ΔV / ΔI across every frequency where current changes. No single capacitor can hold that impedance flat from DC to GHz, so engineers stack contributions:
Bulk capacitors (10–100 µF) handle low-frequency, high-charge demands near the regulator.
Mid-range ceramics (0.1–1 µF) cover the megahertz band.
Small high-frequency caps (1–100 nF) handle the fastest edges, placed right at the chip.
The power/ground plane pair itself behaves as a very-high-frequency capacitor with near-zero inductance.
The PDN as a graded ladder: bulk caps near the regulator, high-frequency caps at the die.
Placement proximity: the loop is everything
When a capacitor sources transient current, that current flows out of the cap, through a via into the power plane, across to the chip, and back through ground. The area this loop encloses sets the loop inductance, and inductance — not capacitance — limits how fast the cap can respond. The impedance of that parasitic inductance is Z = 2πfL, so even a few nanohenries become ohms at high frequency.
Practical rules for minimizing the loop:
Distance: place high-frequency caps within a few millimetres of the power pin — ideally directly adjacent, and for BGAs often on the opposite side of the board under the ball field.
Short, fat connections: use wide, short traces (or direct pad-to-pad) from the cap to its vias. Thin necked-down traces add inductance.
Via placement: drop the power and ground vias as close to the capacitor pads as possible. Via-in-pad or vias flanking the pad beat a via on a stub.
Multiple vias: two vias per pad roughly halve the via inductance.
Tight pair spacing: keep the power via and ground via close together so their fields cancel and mutual inductance drops.
Good vs. poor placement, side by side
The animated diagram below shows the same capacitor connected two ways. On the left the loop is small and the charge pulse reaches the chip cleanly; on the right a long trace and a remote via stretch the loop, and the same pulse arrives degraded.
Charge travels the loop. A tight loop (left) means low inductance and a fast, clean response; a stretched loop (right) rings and sags.
Value selection: self-resonance and mounting inductance
Every real capacitor is a series RLC: capacitance C, equivalent series resistance (ESR), and equivalent series inductance (ESL) plus the mounting inductance of the board. It is only capacitive below its self-resonant frequency (SRF); above SRF it looks inductive and stops decoupling. Smaller case sizes and smaller values resonate higher, which is why the tiny caps live closest to the chip.
Choose values so adjacent SRFs overlap and keep PDN impedance under the target across the band — this is why you see, say, 10 µF + 100 nF + 10 nF rather than ten identical 100 nF parts.
Prefer the smallest footprint (e.g. 0402/0201) for the highest-frequency caps; package ESL often matters more than the capacitance.
Be wary of blindly paralleling many different values — poorly chosen combinations create anti-resonance peaks where impedance spikes between two caps' resonances. Simulate the PDN or follow the IC vendor's decoupling table.
Account for DC-bias derating in class-II ceramics (X5R/X7R): a 10 µF part can lose half its capacitance at rated voltage.
A real capacitor is capacitive below its self-resonant frequency and inductive above it.
Learn this hands-on
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List every power pin and its vendor-recommended cap count and values.
Place the smallest-value cap first, hard against the pin; work outward to larger values.
Give each cap its own short via pair to the power/ground plane pair — never share a long trace stub.
Keep the power and ground planes adjacent and close in the stackup to add plane capacitance and shrink loop area.
For BGAs, mirror HF caps under the device; for QFPs, flank each side of the package.
Verify with a PDN impedance plot against your target before routing signals.
decoupling capacitor placement — FAQ
How close should a decoupling capacitor be to the IC?
As close as the layout physically allows — high-frequency bypass caps belong within a few millimetres of the power pin, often directly under a BGA. The goal is minimum loop inductance, so closeness plus short vias matter more than the exact distance number.
Does a bigger capacitor always decouple better?
No. Above its self-resonant frequency a capacitor behaves as an inductor and stops decoupling. Large values are slow and belong near the regulator; the fastest transients need small-value, small-package caps at the pin.
Why use several different capacitor values instead of one?
Each value is only low-impedance near its resonance. Spreading values keeps the PDN impedance below target across a wide frequency band, from the bulk region up to the fast switching edges.
What is anti-resonance in decoupling?
When two capacitors of different values are paralleled, the inductive branch of one and the capacitive branch of the other can resonate, creating a sharp impedance peak between their SRFs. Careful value selection or PDN simulation avoids placing a peak where the chip has energy.