In short: Signal integrity in PCB is the discipline of keeping a digital or analog waveform clean as it travels across copper traces. Reflections, crosstalk and ringing all come from impedance that is not controlled or not matched, and they are tamed with proper trace geometry, return paths and termination. Eye diagrams are the single best lab tool for judging whether the link still works.
Signal integrity in pcb describes how faithfully an electrical signal keeps its intended shape, timing and voltage levels as it propagates from a driver, along a copper trace, through vias and connectors, to a receiver. At low speeds a trace behaves like a simple wire, so almost anything works. As edge rates get faster, even a 5 cm trace starts behaving like a transmission line, and the physics of reflections, coupling and loss begin to distort the bits. When those distortions grow large enough, the receiver samples the wrong value and the system sees random bit errors that are maddening to debug.
The key intuition is that speed is set by edge rate, not clock frequency. A 50 MHz clock with a 200 ps rise time contains energy well past 1 GHz, and it is that fast edge, not the slow clock, that excites every integrity problem on the board.
Every trace-plus-reference-plane pair has a characteristic impedance (Z₀), typically 50 Ω single-ended or 100 Ω differential. It is set by trace width, dielectric height, copper thickness and the dielectric constant (Dₖ) of the laminate. A signal travelling down a uniform trace sees a constant impedance and nothing is reflected. The moment the impedance changes — a stub, a connector, a via, a width step — part of the energy bounces back. Controlling Z₀ from end to end is therefore the foundation of good signal integrity in pcb design.
When a fast edge hits an impedance discontinuity, a fraction of the wave reflects. The reflection coefficient Γ = (Zₗ − Z₀) / (Zₗ + Z₀) tells you how much. An open-ended trace (Zₗ = ∞) reflects the entire edge back positively; a shorted end reflects it inverted. These reflections bounce between driver and receiver, adding and subtracting from the main signal to produce ringing — the overshoot, undershoot and damped oscillation you see on a scope. Ringing is not just ugly: overshoot can forward-bias input protection diodes, and settling time eats into your timing budget.
Termination forces the far or near end to look like Z₀ so no energy reflects. The common schemes are:
Choosing the scheme is a trade of power, part count and topology, but the goal is always the same: present a matched impedance so the reflection coefficient approaches zero.
Crosstalk is unwanted energy that couples from an active (aggressor) trace onto a quiet (victim) trace through mutual capacitance and mutual inductance. Capacitive coupling injects current proportional to dV/dt; inductive coupling injects voltage proportional to dI/dt. Because the two mechanisms add at the near end and partly cancel at the far end, engineers distinguish NEXT (near-end crosstalk) from FEXT (far-end crosstalk). The practical fixes are geometric and discipline-driven:
A plane split or a gap under a trace forces the return current to detour, which both raises impedance locally and dramatically widens the loop that couples into neighbours — one of the most common real-world signal integrity in pcb failures.
An eye diagram overlays thousands of bit transitions on top of each other, triggered on the clock. A wide-open "eye" means the receiver has clear voltage and timing margin; a collapsing eye means jitter, inter-symbol interference or reflections are closing the window. The vertical opening is your noise margin, the horizontal opening is your timing margin, and the thickness of the crossing points reveals jitter. High-speed standards (USB, PCIe, DDR, SerDes) all publish a mask — a forbidden keep-out polygon the eye must not intrude on.
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Explore CourseTron Courses →It depends on edge rate, not clock speed. Once a trace is electrically longer than about one-sixth of the rise time, reflections matter. On FR-4 that can be just a few centimetres for sub-nanosecond edges, so even "slow" clocks with fast drivers need attention.
Reflection is energy bouncing back along the same trace because of an impedance mismatch. Crosstalk is energy coupling from one trace onto a different, neighbouring trace through mutual capacitance and inductance. One is a self-problem; the other is a neighbour problem.
For a single point-to-point CMOS link, series (source) termination is usually best: it is cheap and draws no static current. For multi-drop buses or where the receiver must be held at a defined level, parallel or Thevenin termination gives stronger matching at the cost of power.
Look at the opening. A tall, wide, clean eye means healthy voltage and timing margin. If the eye is closing vertically you have noise or loss; if it is closing horizontally you have jitter or inter-symbol interference. Check that the trace clears the standard's mask.
Related: impedance matching in PCB · Glossary · all courses.