In short: Differential pair routing carries a signal as two equal-and-opposite traces so noise cancels and the receiver reads only the difference between them. Getting it right means tight coupling, controlled differential impedance (usually 90 or 100 ohms), and disciplined length matching so both intra-pair and inter-pair skew stay small.
Differential pair routing is the practice of laying out two signal traces that carry the same information with opposite polarity: when one trace swings high, the other swings low by the same amount. The receiver at the far end does not look at either trace against ground; it looks at the voltage difference between them. This single idea is what makes USB, HDMI, PCIe, Ethernet, LVDS, DDR strobes and MIPI reliable at gigabit speeds.
Because any external noise, ground bounce, or crosstalk tends to couple into both traces almost equally (common-mode), subtracting one from the other cancels that shared disturbance. The wanted signal, which is equal and opposite (differential-mode), is preserved and effectively doubled. The payoff only appears when the two traces are treated as one coupled structure rather than two independent nets.
Coupling is the electromagnetic interaction between the two traces of the pair, set mainly by how close they run to each other relative to their height above the reference plane. Routing them with a tight, constant spacing does three useful things: it keeps the differential impedance stable, it concentrates the return current between the pair, and it makes external noise couple symmetrically so it cancels.
There are two coupling styles. Edge-coupled pairs run side by side on the same layer and are the most common. Broadside-coupled pairs sit one above the other on adjacent layers, useful when horizontal room is scarce but harder to fabricate consistently. In both cases the golden rule is that the gap between P and N must not wander: every change in spacing is a local impedance discontinuity that reflects energy and degrades the eye.
High-speed interfaces specify a target differential impedance — typically 90 Ω for USB and DDR, or 100 Ω for PCIe, Ethernet and most LVDS links. The PCB fabricator achieves this through the stackup: trace width, the spacing between the pair, the dielectric height to the nearest plane, and the dielectric constant (Dk) of the laminate all interact.
Practical guidance:
Skew is timing error from unequal path length, and there are two kinds. Intra-pair skew is the length mismatch between P and N of the same pair. When one trace is longer, its edge arrives late, so the two signals are no longer perfectly opposite at the receiver. That converts wanted differential energy into common-mode noise, which hurts both signal integrity and EMI. Intra-pair matching is the tight one — often held to a few mils (thousandths of an inch).
Inter-pair skew is the length difference between different pairs that must stay aligned, such as the lanes of a parallel bus or a clock/strobe versus its data. Its budget is looser than intra-pair but still matters for bus timing. The two budgets are independent, and a common mistake is matching lanes to each other while letting P and N inside a lane drift apart.
Length matching is how you drive skew toward zero. The tool of choice is a short serpentine (accordion) added to the shorter trace. A few rules keep serpentines from causing new problems:
Remember that matching is about time of flight. Copper length is a good proxy only when both traces travel through identical dielectric on the same layer, which is exactly why staying on one layer, tightly coupled, with a solid reference plane, makes the whole job easier.
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Explore CourseTron Courses →Intra-pair skew is the length (timing) mismatch between the two traces P and N within one pair; it should be held very tight because mismatch turns differential signal into common-mode noise. Inter-pair skew is the mismatch between separate pairs or lanes that share a timing budget, such as a data lane versus its clock; its tolerance is usually looser.
Follow the interface spec. USB and DDR commonly use 90 Ω differential, while PCIe, Ethernet and LVDS generally use 100 Ω. Always confirm the exact figure in the device and standard documentation and solve the stackup to hit it.
The return current flows in the plane directly beneath the traces. A split or gap forces that current to take a longer detour, which raises local impedance, creates reflections, and radiates EMI. Keep an unbroken plane, and add stitching vias when changing layers.
Add serpentines when the intra-pair length difference exceeds the budget set by your edge rate and data rate — faster edges demand tighter matching. For slow or short links the mismatch may be negligible; for multi-gigabit links even a few mils can matter.
Related: impedance matching in PCB · Glossary · all courses.