In short: Epitaxy grows a new single-crystal layer that inherits the atomic lattice of the wafer beneath it, letting fabs add defect-free doped silicon, SiGe source/drains, and deliberately strained channels that modern FinFET and GAA transistors cannot ship without.
Epitaxy is one of the quietest but most decisive steps in a modern CMOS flow. Where thermal oxidation consumes silicon to form an amorphous insulator, epitaxy does the opposite: it adds crystalline material that is lattice-registered to the substrate. "Epi" (from the Greek epi-taxis, "arrangement upon") means the deposited atoms line up on the template the wafer provides, so the film is effectively an extension of the single crystal rather than a separate polycrystalline or amorphous layer.
Why grow a crystal when you already have a wafer?
A polished Czochralski wafer is already excellent silicon, so engineers often ask why fabs bother depositing more of it. Three reasons dominate:
- Purity and control. An epitaxial layer can be doped far more precisely than the bulk, with an abrupt, independently set profile. A classic example is a lightly doped n-type epi (say 1015 cm-3) grown on a heavily doped n+ substrate (1019 cm-3) for power and BiCMOS devices.
- Latch-up suppression. The same p-epi-on-p+ structure lowers substrate resistance and chokes the parasitic thyristor that causes CMOS latch-up.
- Band and strain engineering. By growing alloys such as SiGe or SiGe:B, fabs put a material with a different natural lattice constant where they want it, creating controlled mechanical strain that boosts carrier mobility.
Key fact: Germanium's lattice constant is about 4.2% larger than silicon's (5.658 Å vs 5.431 Å). A pseudomorphic Si0.75Ge0.25 film grown on silicon is squeezed to match, storing roughly 1% compressive strain in the channel.
Homoepitaxy vs heteroepitaxy
Homoepitaxy grows the same material as the substrate — silicon on silicon — and is the workhorse for buffer and device layers. Heteroepitaxy grows a different material, like SiGe on Si, GaN on sapphire, or III-V channels on silicon. Heteroepitaxy is where lattice mismatch becomes both the tool and the enemy: a small mismatch stores useful strain, but past a critical thickness the film relaxes by nucleating misfit dislocations that destroy device yield.
How the layer is actually grown
The dominant technique in high-volume logic and memory fabs is chemical vapor deposition (CVD) epitaxy, usually reduced-pressure CVD (RPCVD) in single-wafer lamp-heated reactors from vendors such as Applied Materials (Epi Centura) or ASM (Intrepid/Epsilon). Silicon precursors like silane (SiH4), dichlorosilane (SiH2Cl2, "DCS") or trichlorosilane crack at the hot wafer surface; germane (GeH4) is co-flowed for SiGe, and diborane (B2H6) or phosphine supplies in-situ dopants. Typical temperatures run 600-800 °C for selective SiGe and up to ~1050 °C for blanket silicon epi.
Molecular beam epitaxy (MBE) trades throughput for atomic precision, using ultra-high-vacuum effusion cells; it is mostly a research and III-V tool rather than a CMOS production step. The key quality metric for all of them is defect density — stacking faults, hillocks and the misfit dislocations that appear once strain exceeds the critical thickness.
Selective epitaxy and SiGe source/drain
The step that made epitaxy a star of the sub-45 nm era is selective epitaxial growth (SEG) of raised, strained source/drains. In a PMOS transistor, the silicon in the source and drain regions is recessed and then embedded SiGe (eSiGe) is grown selectively — the chlorine chemistry etches away any nuclei on the oxide/nitride spacers so the alloy deposits only in the exposed silicon windows. Because SiGe wants a bigger lattice, it pushes inward on the channel, applying uniaxial compressive strain that raises hole mobility by tens of percent. NMOS gets the mirror-image treatment with tensile silicon or SiC source/drains.
Key fact: Intel introduced eSiGe at the 90 nm node (2003) and has pushed Ge fractions past 50% in later nodes; today's GAA/nanosheet devices still rely on SiGe epi both for strain and as the sacrificial layer that is later etched to release the channels.
| Layer | Typical composition | Purpose |
|---|---|---|
| Device epi | Lightly doped Si on n+/p+ | Clean channel, latch-up control |
| eSiGe S/D (PMOS) | Si₁₋ₓGeₓ:B, x≈0.3-0.55 | Compressive channel strain, low contact R |
| Tensile S/D (NMOS) | Si:C or Si:P | Tensile strain, electron mobility |
| GAA sacrificial | SiGe/Si superlattice | Removed to release nanosheets |
Strain, mobility and where simulation comes in
Strain works because it splits the conduction and valence bands and reshapes the carrier effective mass, lowering scattering. Getting the magnitude and sign right across billions of transistors is not something you tune empirically on silicon — it is modeled first. TCAD tools such as Synopsys Sentaurus (Process + Device) simulate the epi recess shape, the stress field eSiGe imposes, and the resulting mobility and drive-current gain; Siemens EDA and Cadence provide the downstream parasitic and reliability analysis once the strained device is characterized. This is where a VLSI engineer sees epitaxy on screen long before touching a wafer.
Common failure modes
- Relaxation / misfit dislocations when SiGe exceeds its critical thickness for a given Ge fraction.
- Loading effects in selective growth: narrow source/drain windows grow at a different rate than wide ones, skewing device matching.
- Facet formation at the edge of the epi window, which changes the stress transferred to the channel.
- Autodoping, where dopant out-diffuses from a heavily doped substrate into the "clean" epi.
Epitaxy connects directly to the rest of the front-end flow you study in our ion implantation and oxidation modules — the epi layer defines the crystal you then implant, oxidize and pattern. For a hands-on view of how these strained devices are designed and verified in real EDA tools, our partner design house Avecas VLSI design services runs production flows on exactly this technology.
Want to go from "what is epitaxy" to reading TCAD stress plots and strained-device datasheets with confidence? Build the full front-end picture in the CourseTron Nano Fabrication course.
Frequently asked questions
Is epitaxy the same as deposition?
No. All epitaxy is deposition, but ordinary deposition (like CVD oxide or sputtered metal) produces amorphous or polycrystalline films. Epitaxy specifically produces a single-crystal film registered to the substrate lattice, which requires a clean, crystalline starting surface and the right temperature window.
Why use SiGe instead of just more silicon?
Germanium's larger lattice constant lets engineers store controlled strain in the channel, and SiGe also offers lower source/drain contact resistance and tunable band offsets. Pure silicon source/drains cannot provide the mobility boost that strain gives.
What limits how thick a SiGe layer can be?
The critical thickness, set by the Matthews-Blakeslee relation. Below it the film stays pseudomorphic (strained); above it the stored strain energy is relieved by misfit dislocations, which degrade the device. Higher Ge fraction means a thinner critical thickness.
Do GAA/nanosheet transistors still use epitaxy?
More than ever. The Si/SiGe superlattice that defines the nanosheets is grown epitaxially, and the SiGe is later selectively etched to release the channels — plus the strained source/drains are still epitaxial.