Wafer sort vs final test

In short: Wafer sort (CP) probes bare die on the wafer at room-ish temperature to kill gross defects before the expensive packaging and assembly step, while final test (FT) exercises the fully packaged part across voltage and temperature corners to guarantee the shipped device meets its datasheet — the two stages catch different failure populations and together define your test cost and yield.

Two gates, one goal: ship only known-good silicon

Every digital, analog, or mixed-signal product passes through at least two electrical screens on its way from a 300 mm wafer to a tray of packaged parts. The first is wafer sort — also called circuit probe (CP) or wafer-level test. The second is final test (FT), performed after the die is diced, attached, bonded, and molded into a package. Confusing the two is a classic interview trip-up, because they share equipment families (Advantest V93000, Teradyne UltraFLEX) and pattern sets, yet they answer very different questions.

Wafer sort asks: "Is this die worth the ~$1–3 it costs to package?" Final test asks: "Does this packaged part meet every spec I printed on the datasheet, at every corner the customer will see?" The economics flow directly from that distinction.

What wafer sort catches

At sort, a probe card (cantilever, vertical/Cobra, or MEMS) lands dozens-to-thousands of needles on the die's bond pads or bumps. The prober steps the wafer under the card; the ATE applies DC continuity/leakage tests, scan-based structural tests (stuck-at and transition ATPG from Synopsys TestMAX or Siemens Tessent), memory BIST, and a reduced functional set. Sort is excellent at finding:

• Gross process and lithography defects — opens, shorts, particle-induced bridging.
• Parametric die that fail at wafer corners — leaky transistors, slow paths flagged by Fmax screens.
• Memory bit failures repairable by on-chip redundancy (BISR), fixed before packaging.
• Spatial yield signatures — edge-of-wafer rings, center clusters that feed the wafer map back to the fab.

A wafer map is diagnostic gold: a donut-shaped fail pattern points at a CMP or deposition non-uniformity, not a random defect. You lose that spatial fingerprint entirely once die are packaged and shuffled into trays.

Sort is usually run single-corner (nominal V, ~25–30 °C ambient, with self-heating) because its job is a cost gate, not datasheet sign-off. Known-good-die (KGD) flows for chiplets and HBM stacks push harder — they may add burn-in or at-speed test at sort because there is no second chance once the die is inside a 2.5D package.

What final test catches

After assembly, FT runs the part in a handler (gravity or pick-and-place) that docks it to a load board socket and forces it across PVT corners. This is where you catch what sort structurally cannot:

• Assembly-induced defects — bond-wire opens, cracked die, delamination, solder-ball voids.
• Package parasitics — lead inductance and bump resistance that only matter at full I/O speed.
• Temperature-dependent failures — hot (85–125 °C) and cold (−40 °C) corners expose timing and leakage escapes.
• Full functional / at-speed / high-speed I/O — SerDes BER, DDR eye margin, loopback that needs real package pins.

Roughly 60–80% of field returns trace to defects that are only testable after packaging — which is exactly why you cannot skip FT even on a mature node with 95%+ sort yield.

Flow, equipment, and the handoff

The two stages differ in almost every mechanical detail, even when the test program shares a code base:

Both run on the same ATE families — an Advantest V93000 or Teradyne UltraFLEX can be configured for either stage — and both consume ATPG patterns generated by Synopsys TestMAX or Siemens Tessent, with DFT structures (scan, compression, MBIST) inserted during synthesis. The art is sharing that pattern set while re-timing it: sort may clock scan shift conservatively, while FT runs at-speed transition faults to catch package-limited timing.

The cost argument — why sort exists at all

Test is pure yield loss if it passes everything, so engineers justify each stage economically. Packaging a die costs real money: substrate, wire bond or flip-chip bump, mold compound, and handling can run $0.50 to several dollars per unit, and far more for advanced 2.5D/3D or flip-chip BGA. Sort exists to avoid spending that on die that will never work.

Consider 1,000 die at 90% sort yield. Skipping sort means packaging all 1,000 — you spend ~$2,000 in assembly, then FT rejects ~100, having wasted ~$200 packaging dead die. Run sort first (say $0.15/die probe cost = $150), ink the 100 bad die, and you package only 900 — the $200 of wasted assembly collapses to the sort cost, and your FT handler throughput improves because it isn't chewing on guaranteed rejects. The crossover favors sort heavily as packaging cost and defect density rise, which is why advanced nodes and KGD/chiplet flows invest more at sort, not less.

Rule of thumb: the later a defect escapes, the ~10× more it costs to catch. Die-level → package-level → board-level → field. Sort and FT are two rungs of that escalating-cost ladder.

Where this fits in your post-silicon toolkit

Wafer sort and final test are the production bookends of a larger discipline that also includes burn-in, system-level test (SLT), characterization, and diagnosis. If you are building that mental model, start with our deep dive on wafer sort testing fundamentals, then connect it to DFT scan-chain basics to see how the patterns these testers run are built in at design time. For teams productizing silicon, the hand-off from test engineering to Avecas VLSI design and DFT services is where test cost and coverage targets get negotiated against area and schedule.

Want to run a real ATPG-to-ATE flow and read a wafer map yourself? Explore CourseTron's hands-on post-silicon and DFT validation courses.

Frequently asked questions

Can you skip wafer sort if yield is very high?

Rarely. Even at 98% sort yield, skipping it ships gross-defect die into a packaging line and clogs the FT handler with guaranteed rejects. For KGD and chiplet flows it is mandatory — a bad die inside a 2.5D package ruins every other die in that package.

Why does final test use temperature corners but sort usually doesn't?

Sort is a cost gate: its job is to find packaging-unworthy die cheaply, so it runs mostly at one corner. FT must guarantee the datasheet across the customer's operating range, so it adds hot and cold insertions where timing and leakage escapes appear.

Do sort and final test use the same test program?

They often share the same ATPG patterns and DFT structures (scan, compression, MBIST from TestMAX or Tessent) and even the same ATE family, but the programs are retimed and re-scoped — sort trims to a gross-defect subset, FT adds at-speed and high-speed I/O tests the package enables.

What is a "test escape" and which stage owns it?

A test escape is a defective part that passes test and reaches the customer. Sort owns escapes of process defects; FT owns assembly, package, and temperature-dependent escapes. Defect-per-million (DPM) targets and burn-in exist to drive escapes down further.