In short: Semiconductor testing screens every die from wafer sort (probe test on the raw wafer) through final package test, applying structural and functional patterns against a test program to sort good parts from bad and bin survivors by speed and grade.
When a 300 mm wafer rolls off a modern fab line carrying perhaps 600 copies of a chip, not one of those die has yet been proven to work. Defects are inevitable: a single stray particle, a stuck via, or a marginal transistor can kill a die. Post-silicon test is the discipline that separates the parts you can ship from the ones you cannot, and it is where profit margin is quietly won or lost. This article walks the full flow from wafer sort to final test and binning, with the "why" behind each step.
Why we test at all: yield and escape
Two numbers dominate test economics. Yield is the fraction of die that pass; test escape (measured in DPPM, defective parts per million) is the fraction of bad parts that slip through. An automotive customer may demand sub-10 DPPM, so a flow that catches 99.99% of defects is still failing. The tension is that more test time means more cost per part on expensive automated test equipment (ATE) from Advantest or Teradyne, where a tester-hour can run tens of dollars. Every second of test time is weighed against the defects it catches.
A high-end ATE system (e.g. Teradyne UltraFLEX or Advantest V93000) can cost $2–5M. On a parallel site count of 32, shaving 100 ms of test time per die across a million-unit volume saves meaningful tester capacity — which is why test time is engineered as aggressively as the silicon.
The end-to-end flow
Wafer sort (probe / CP)
At wafer sort — also called circuit probe (CP) or wafer-level test — a probe card with hundreds of needles or vertical MEMS tips lands on the die's bond pads or bumps while it is still part of the wafer. The ATE runs a subset of the test program: continuity checks, power shorts, static current (IDDQ), and the fastest-to-catch structural tests. The goal is to find gross defects before spending money to dice and package a dead die. The output is a wafer map — a grid recording pass/fail and bin number per die. Historically bad die were physically inked; today an electronic map (SINF/STDF) travels downstream so assembly skips the failures.
Known-good-die (KGD) requirements for 2.5D/3D stacks (HBM on an interposer, chiplets) make sort far more rigorous: a single bad die in a stack scraps the whole expensive module, so sort coverage approaches final-test rigor.
Structural vs. functional test
Two philosophies coexist. Functional test exercises the chip the way a system would — boot it, run instructions, read a result. It is intuitive but hard to achieve high defect coverage and expensive to develop. Structural test instead targets the fabric: scan chains (flip-flops stitched into shift registers) let the ATE load any state, pulse the clock, and capture the response. Automatic test pattern generation (ATPG) tools — Synopsys TestMAX (formerly TetraMAX), Siemens EDA Tessent, or Cadence Modus — generate patterns that provably cover modeled defects.
- Stuck-at: a node frozen at 0 or 1. The baseline fault model; 98–99%+ coverage is expected.
- Transition/at-speed delay: catches too-slow paths, run with launch-on-capture at functional frequency.
- IDDQ: measures quiescent current to flag bridging defects a logic test might miss.
- Cell-aware / bridging: models defects inside standard cells, important at 7 nm and below.
Design-for-test (DFT) structures — scan compression, boundary scan (JTAG, IEEE 1149.1), and built-in self-test (BIST) for memories (MBIST) and logic (LBIST) — are inserted during design precisely so these patterns can be applied efficiently. Building and tuning the patterns and limits that the ATE applies is the subject of our companion guide on test program development.
Burn-in and reliability stress
Some defects are latent — they only surface after hours of operation. Burn-in subjects packaged parts to elevated voltage and temperature (e.g. 125 °C) to accelerate the "infant mortality" region of the bathtub curve, weeding out parts that would fail in the customer's first weeks. For high-reliability and automotive (AEC-Q100) parts this is mandatory; for cost-sensitive consumer parts it may be reduced or replaced by statistical screening such as PAT (part average testing).
Final test and binning
After packaging (and optional burn-in) the part returns to an ATE in a handler that presents it to a socket. Final test re-runs structural coverage plus the tests only possible on a packaged part: full at-speed performance, analog/mixed-signal measurements, I/O characterization, and thermal behavior. Survivors are then binned. Binning is not merely pass/fail — it is product grading. A CPU that runs correctly at 5.0 GHz and within a power envelope is sold as a premium SKU; the same die that only passes at 4.2 GHz is a lower SKU; one with a defective core but seven working cores becomes a different part number entirely. This "speed binning" and fused feature disabling is how one physical design yields a whole product stack.
| Bin | Meaning | Disposition |
|---|---|---|
| Bin 1 | Pass, top grade | Premium SKU |
| Bin 2–3 | Pass, lower speed/power | Value SKU |
| Bin 4 | Partial (core/feature fused off) | Harvest SKU |
| Bin 5+ | Fail (open, short, delay, IDDQ…) | Scrap / FA |
Every result is logged to a STDF (Standard Test Data Format) file. Test engineers mine this with yield-analytics platforms to build Pareto charts of failure causes, drive wafer-map signatures back to a fab process step, and tighten limits. The data loop between test and fab is as valuable as the sorting itself. Teams building silicon in India, such as the design-services group at Avecas VLSI design services, lean on exactly this post-silicon telemetry to qualify a new tape-out.
Putting it together: a worked example
Consider a 7 nm networking SoC. At sort, IDDQ and scan stuck-at patterns (compressed 50:1 by Tessent) run in ~400 ms per die and remove 8% of die with hard defects. Good die are assembled into a flip-chip BGA. Automotive-grade units get 48 h burn-in. Final test adds at-speed transition patterns at 1.2 GHz plus SerDes BER characterization, taking ~2 s. Parts passing all SerDes lanes bin as the full part; those failing one lane group are fused to a reduced-port SKU. Final yield after both insertions is 86%, with escapes held under 50 DPPM by the IDDQ+cell-aware combination.
To go deeper on the design-side structures that make all this possible, see our walkthrough of design-for-test (DFT) fundamentals, and browse the full CourseTron course catalogue for hands-on labs.
Want to run ATPG, debug a failing scan chain, and build a real binning flow on industry tools? Join the CourseTron Post-Silicon Validation & Test course and learn it hands-on. Prefer instructor-led cohorts? Our partner ChipXpert VLSI training runs them too.
Frequently asked questions
What is the difference between wafer sort and final test?
Wafer sort tests die while still on the wafer to avoid packaging known-bad parts; final test tests the finished package and adds measurements only possible once packaged, such as full at-speed performance, thermal behavior, and high-speed I/O.
What does "binning" mean?
Binning assigns each tested part a category. Beyond pass/fail, it grades passing parts by speed and power so one physical die design can be sold as several SKUs, including harvest parts with defective blocks fused off.
Why use structural (scan) test instead of just running the chip?
Functional test is hard to scale to high, provable defect coverage. Scan plus ATPG gives measurable coverage of modeled faults (stuck-at, transition, bridging) and far shorter development time, which is why modern digital parts rely on it.
What is IDDQ testing?
IDDQ measures the quiescent (leakage) supply current when the circuit is static. Abnormally high current signals bridging or gate-oxide defects that a purely logical test might not detect.