In short: Power MOSFETs and IGBTs are qualified by pushing them to their electrical limits on a curve tracer or ATE — ramping drain/collector voltage until avalanche to confirm breakdown rating, forcing a known current to measure on-resistance or saturation drop, and switching real load current under a clamped-inductive-load rig to capture turn-on/turn-off energy and safe-operating-area margin.
A logic chip either computes the right answer or it does not. A power device is different: it has to survive hundreds of volts, tens of amperes and the thermal pulse of every switching edge for a decade in the field. That makes power-semiconductor test less about "pass/fail logic" and more about measuring continuous physical quantities right up to the edge of destruction. This article walks through the three pillars every post-silicon power engineer measures — breakdown voltage, on-resistance (RDS(on)) or saturation voltage (VCE(sat)), and dynamic switching behaviour — and the equipment and gotchas behind each.
Why power-device test is its own discipline
A 650 V silicon-carbide MOSFET or a 1200 V IGBT module spends its life dissipating real power. Two parameters dominate its usefulness: how much voltage it blocks when off, and how little it drops when on. Everything else — gate charge, thermal resistance, switching loss — flows from the physics that set those two. Because the measurements involve large currents and lethal voltages, the rigs are built around high-power source-measure units (SMUs), curve tracers such as the classic Tektronix 371 / Keysight B1505A power-device analyzer, and double-pulse switching benches rather than the small-signal ATE used for CMOS logic.
A modern power curve tracer like the Keysight B1505A can force up to 3,000 V and 1,500 A pulsed on a single device — numbers that would vaporise a conventional parametric tester.
1. Breakdown voltage (BVDSS / V(BR)CES)
Breakdown is measured with the device off. For a MOSFET you short gate to source (VGS = 0), then ramp drain voltage while monitoring leakage current. The breakdown rating is the voltage at which that leakage hits a defined threshold — typically 250 µA for a 600 V part. Below breakdown you are characterising the drain-leakage IDSS; at breakdown the junction enters avalanche and current rises almost vertically.
The practical art is doing this without destroying the part. Engineers ramp in a current-limited mode: the SMU is set to force a small compliance current (say 1 mA) and report the voltage it needs. That way the device sits at the knee of the avalanche curve instead of running away thermally. A 100 V-rated trench MOSFET will typically show a true BV of 110–125 V, the margin the vendor designs in so the datasheet number is guaranteed across temperature. Breakdown has a positive temperature coefficient in silicon, so the part is often tested hot (125 °C) where BV is highest and leakage worst.
2. On-resistance and saturation voltage
With the device fully on, you want the smallest possible voltage drop. For a MOSFET this is RDS(on): drive the gate hard (e.g. VGS = 10 V), force a specified drain current, and divide the measured VDS by that current. A 100 V, 120 A automotive MOSFET might spec 4.5 mΩ at 25 °C — meaning at 60 A it drops only 270 mV but still dissipates 16 W. RDS(on) roughly doubles from 25 °C to 150 °C, so it is always characterised across temperature on a thermal chuck.
IGBTs do not have a resistive channel; they behave like a transistor in series with a diode, so the on-state figure is a saturation voltage VCE(sat) — typically 1.5–2.0 V at rated collector current, largely independent of current. This is why IGBTs win at high voltage and high current (the fixed ~1.8 V drop beats a MOSFET's I²R at hundreds of amps) while MOSFETs win at low voltage.
| Parameter | Power MOSFET | IGBT |
|---|---|---|
| On-state metric | RDS(on) (mΩ) | VCE(sat) (V) |
| Drop at rated current | I × R (scales with I) | ~1.5–2.0 V (nearly flat) |
| Sweet spot | < 250 V, fast switching | > 600 V, high current |
| Temp. coeff. of on-drop | Positive (easy paralleling) | Often slightly negative near rating |
A four-terminal (Kelvin) connection is mandatory here: at milliohm resistances, the probe and lead resistance would swamp the measurement, so force and sense lines are separated right at the package. This is the single most common rookie error in a power lab — reading 8 mΩ on a 4 mΩ part because of cable drop.
3. Dynamic switching under high current
Static DC parameters tell you nothing about loss during the microseconds of a switching edge, where most heat in a motor drive or SMPS is actually generated. The standard rig is the double-pulse test (DPT) with a clamped inductive load — an inductor represents the motor winding, and a freewheeling diode clamps the voltage.
The first gate pulse ramps current in the inductor to the target (say 50 A); the gap between pulses holds it; the second pulse's rising and falling edges are where you capture everything. With a high-bandwidth oscilloscope, a coaxial-shunt or Rogowski current probe and a high-voltage differential probe, you record turn-on energy Eon, turn-off energy Eoff, the reverse-recovery spike of the diode, and dV/dt. These energies, multiplied by switching frequency, give the switching power loss that the heatsink must remove.
In a double-pulse test the energy that matters is captured in under 1 µs — which is why a 500 MHz-plus scope and a de-skewed current probe are non-negotiable; a 20 ns de-skew error between voltage and current traces can mis-state Eoff by 30%.
Every switching event must stay inside the device's safe operating area (SOA) — the V–I envelope bounded by current limit, voltage limit and the thermal/second-breakdown line. Reliability teams also run unclamped inductive switching (UIS) to rate avalanche energy, and HTRB (high-temperature reverse bias) and power-cycling stress to confirm the part survives years of thermal fatigue. On the design side, the same SPICE/foundry models that predicted these curves are correlated against silicon using tools from the Synopsys and Cadence device-modelling flows, while Siemens EDA's reliability verification closes the loop between layout and field robustness.
Putting it together in a test plan
A production flow typically runs the fast DC gates first (breakdown, leakage, RDS(on), threshold) on every part at wafer sort and final test, then pulls samples for the slower dynamic and reliability characterisation. Characterisation engineers build the full curve library; product engineers pick the handful of correlated DC tests that screen the same failure modes at 1/100th the test time. For a deeper treatment of the high-voltage fixturing and guarding that make these measurements trustworthy, see our companion piece on high-voltage device test, and the broader survey of wide-bandgap GaN and SiC characterization.
If you are moving from digital validation into power, the mental shift is this: you are no longer checking bits, you are mapping a device's survival envelope one careful, current-limited sweep at a time. Hands-on bench time with a curve tracer and a double-pulse rig is worth more than any amount of datasheet reading. Our full post-silicon course catalog pairs this theory with lab exercises, and teams building real power products often partner with Avecas design services to bridge characterisation data into silicon-proven designs.
Ready to run your own double-pulse bench? CourseTron's Post-Silicon Power Device Characterization track takes you from curve tracer basics to SOA and UIS testing with real captured waveforms. Explore the course →
Frequently asked questions
Why is breakdown voltage tested with the gate shorted to source?
Shorting VGS to 0 guarantees the channel is fully off so you measure the intrinsic junction breakdown, not a partially-conducting state. Any residual gate voltage would turn the channel on and give a misleadingly low "breakdown".
Why do MOSFETs quote RDS(on) but IGBTs quote VCE(sat)?
A MOSFET conducts through a resistive channel, so its drop scales linearly with current (I × R). An IGBT has a bipolar output stage whose drop is dominated by a p-n junction, staying near 1.5–2 V almost regardless of current — so a saturation voltage describes it better.
What is a double-pulse test and why two pulses?
The first pulse ramps current into an inductive load to the desired test level; the second pulse's edges let you measure true turn-on and turn-off switching energy at that current. One pulse alone could not establish the load current before the edge you want to observe.
What makes SiC and GaN harder to test than silicon?
Wide-bandgap parts switch far faster (tens of V/ns), so parasitic inductance and probe de-skew errors that are negligible for silicon IGBTs dominate the measurement, demanding higher-bandwidth scopes, coaxial shunts and extremely tight fixturing.