In short: Semiconductor testing is the discipline of applying stimuli to a chip and measuring its response to separate good die from defective ones at every stage from wafer to final shipment, so that only parts meeting their datasheet actually reach the customer.
Design and fabrication get most of the attention, but a modern chip is worthless until someone proves it works. That proof is test: the post-silicon discipline that turns millions of fabricated transistors into a quantified yield number and a guaranteed shipping quality. This guide introduces the core vocabulary, the equipment that does the work, and exactly where test sits in the manufacturing flow.
Why test exists: defects are inevitable
No fab achieves 100% yield. A single particle of dust, a mask misalignment, or a marginal transistor threshold can kill a die. On a 300 mm wafer holding, say, 500 large CPU die, it is entirely normal for 20–40% of them to be unsellable at launch. Test is how you find the bad ones before you package and ship them, because the cost of a defect escaping multiplies at every downstream stage.
Rule of 10: a fault that costs ~$0.01 to catch at wafer sort costs roughly ~$0.10 at package test, ~$1 at board level, and $10–$100+ once it is in the customer's system. Catching defects early is the entire economic argument for test.
Where test fits in the flow
Test is not one step — it is a series of gates. The diagram below shows the canonical path from a finished wafer to a shipped, qualified part.
Wafer sort (also called probe or e-sort) happens while die are still on the wafer. A probe card lands fine needles or micro-springs onto the bond pads and the tester exercises each die. Known-bad die are marked (digitally in a wafer map, historically with ink). Only good die move forward to be packaged — there is no point spending packaging dollars on a dead die.
Final test happens after the die is in its package. Here you confirm the part survived assembly and meets its full datasheet across voltage and temperature. Many flows add burn-in — running parts hot and biased for hours to weed out infant-mortality failures — before the final quality-assurance sample gate.
The three questions every test answers
Whatever the stage, a test is trying to resolve one or more of these:
- Structural (DFT): are the transistors and wires manufactured correctly? Scan chains and built-in self-test (BIST) target physical defects — stuck-at, bridging, open faults.
- Functional: does the chip do what the spec says when driven with realistic patterns?
- Parametric: does it meet electrical limits — leakage current, I/O voltage levels, timing (Fmax), power?
Modern digital SoCs lean heavily on structural test because exhaustive functional test is impossible: a design with even a few hundred flip-flops has an astronomically large state space. Scan-based ATPG (automatic test pattern generation) instead targets a fault list and reaches 98–99%+ fault coverage with a tractable number of patterns.
The equipment: ATE, handlers, probers
At the center of a test floor is Automated Test Equipment (ATE) — a large, precise instrument (Advantest and Teradyne dominate this market) that sources stimuli and measures responses on hundreds or thousands of pins at once. Surrounding it:
| Element | Role | Example / detail |
|---|---|---|
| ATE mainframe | Drives patterns, measures DC/AC parametrics, clocks the DUT | Teradyne UltraFLEX, Advantest V93000 |
| Device-under-test (DUT) | The chip being tested | One die or one packaged part |
| Prober | Steps the wafer, aligns die under probe card | Used at wafer sort |
| Handler | Loads/sorts packaged parts, controls temperature | Used at final test; can soak to 125 °C / −40 °C |
| Load board / probe card | Electrical interface between ATE and DUT | Custom per device |
The test program — the software that sequences every measurement and the pass/fail limits — is where product and test engineers spend most of their effort. A good program minimizes test time (directly test cost) while keeping escape rate (bad parts shipped) near zero.
Animated: a scan test shifting through the chip
Structural test works by stitching the chip's flip-flops into long scan chains. A test pattern is shifted in, one capture clock applies it to the logic, and the response is shifted out and compared against the expected value. Watch a single bit propagate:
Tools such as Synopsys TestMAX (formerly DFTMAX/TetraMAX), Siemens EDA Tessent, and Cadence Modus generate these patterns, insert on-chip compression, and build the test logic during the design phase — which is why "DFT" (design-for-test) is a design-side activity even though the payoff is purely post-silicon.
Key metrics you will hear
- Yield — fraction of die that pass. The headline manufacturing number.
- Fault coverage — fraction of modeled faults the pattern set detects. 99% stuck-at is a common target.
- DPPM — defective parts per million shipped. Automotive (ISO 26262 / AEC-Q100) demands single-digit or even sub-1 DPPM.
- Test time — seconds per part on the ATE; a direct driver of unit cost, explored in the economics of test.
These numbers trade off against each other: more coverage usually means more patterns and longer test time, which raises cost. Deciding where to stop is engineering judgment, and it is the heart of the cost-of-test discussion. For a deeper look at how defects are classified and localized after a failure, see our guide on fault models and failure analysis.
Want hands-on depth? CourseTron's post-silicon track walks you from scan insertion to live ATE bring-up with real test programs. Explore the VLSI testing course →
Teams building silicon products often pair in-house test engineering with specialist partners — if you need production DFT and post-silicon validation support, Avecas design services covers that end of the flow.
FAQ
Is wafer sort the same as final test?
No. Wafer sort tests bare die on the wafer and is mainly about not wasting packaging on dead die. Final test tests the packaged part across its full specified voltage and temperature range and is the last gate before the part can ship.
Why not just run functional tests and skip DFT?
Functional vectors can't practically reach every internal node — the state space is far too large and you can't observe deep logic. Structural scan test directly targets a fault list with measurable coverage, so it detects manufacturing defects that functional patterns would miss.
What is burn-in for?
Burn-in stresses parts at elevated voltage and temperature for hours to trigger "infant mortality" failures — weak devices that would otherwise fail early in the field. It is common in high-reliability, automotive, and server parts.
Who makes the test equipment?
The ATE market is led by Advantest and Teradyne. Pattern-generation and DFT software comes from Synopsys (TestMAX), Siemens EDA (Tessent), and Cadence (Modus).