In short: Wafer test (wafer sort) lands a probe card's needles or MEMS tips onto every die on a finished wafer and runs ATE patterns to electrically screen out defective dies before the costly dicing, bonding, and packaging steps.
By the time a 300 mm wafer leaves the fab it may carry several thousand dies, each the product of hundreds of lithography, etch, implant, and deposition steps. Some of those dies are dead—killed by a particle defect, a shorted via, or a marginal transistor. Wafer test, also called wafer sort or probe, is the first electrical gate that separates the living from the dead, so the back-end never spends money packaging silicon that was already scrap.
Why screen at the wafer level at all?
The economic argument is brutal and simple. Packaging a single die—substrate, wire bond or flip-chip bump, mold compound, and the final-test insertion that follows—can cost anywhere from a few cents for a jellybean part to several dollars for a large SoC or an HBM stack. If you package a known-bad die, you throw that money away on top of the wafer cost. Catching the failure at sort, where the incremental test cost is on the order of a few cents of ATE time, is one of the highest-leverage decisions in the whole manufacturing flow.
Rule of ten: the cost of catching a defect roughly multiplies by ten at every downstream stage—wafer → package → board → system → field. A defect caught at sort for pennies becomes a field RMA costing hundreds.
A second, growing motivation is known-good-die (KGD) supply for advanced packaging. When you stack HBM on a logic die or build a 2.5D interposer system, a single bad die can sink a package worth thousands of dollars. Chiplet and multi-die integration cannot work without high-confidence wafer-level screening, which is why KGD has become a boardroom topic, not just a test-engineering one.
The physical setup: prober, probe card, and ATE
Three machines cooperate at a sort cell. The wafer prober (TEL, Accretech, SEMICS) holds the wafer on a temperature-controlled chuck and steps it in X/Y so the right dies sit under the needles. The probe card is the custom interface—a PCB carrying hundreds to tens of thousands of contact tips aligned to the die's bond pads or bumps. The automatic test equipment (ATE)—Advantest V93000 or Teradyne UltraFLEX class testers—supplies power, forces and measures signals, and runs the pattern sets.
Probe card technologies
The probe card is where most of the engineering difficulty lives, because it must make thousands of reliable, low-resistance contacts hundreds of thousands of times. Three families dominate:
- Cantilever (needle) cards—tungsten needles angled onto peripheral pads; cheap, good for low pin count and analog parts.
- Vertical / MEMS cards (FormFactor, Technoprobe)—buckling-beam or micro-spring arrays that handle very high pin counts and fine-pitch area-array bumps, essential for modern SoCs and memory.
- Membrane and advanced spring cards—used where pitch drops below ~40 µm.
Two parameters you will be asked about in interviews: overdrive (how far the chuck pushes up past first contact, forcing the tip to scrub through native oxide and establish a low-resistance contact) and contact resistance (Ccres), which must stay stable across tens of thousands of touchdowns. Tips wear, so cards are cleaned on an abrasive pad on a schedule tracked by touchdown count.
What actually runs during the test
A sort program is a sequence of tests, each with limits, executed in an order chosen to fail cheap-and-fast first. A typical SoC flow:
- Continuity / opens-shorts—force a small current into each pad's ESD diode and check the clamp voltage. A dead needle or an unbonded pad fails here in microseconds.
- Power shorts / IDDQ—quiescent supply current; a gross defect shows up as abnormal leakage.
- Scan / structural test—stuck-at and transition-delay patterns generated by ATPG tools (Siemens Tessent, Synopsys TestMAX, Cadence Modus) shifted through scan chains to exercise internal logic.
- Memory BIST—on-chip engines march through embedded SRAM/DRAM and repair with spare rows/columns where supported.
- Functional / parametric / PLL—at-speed and analog characterization where needed.
Binning and the wafer map
Each die's results collapse into a bin—bin 1 for full pass, other numbers encoding the first failing category (continuity fail, IDDQ fail, scan fail, speed-grade sort, and so on). The accumulated bins form the wafer map, the single most useful diagnostic artifact in the fab: a color-coded grid of every die. Spatial signatures on that map tell you the kind of problem before you ever open a die.
Edge-ring failures usually mean a process gradient (CMP, implant, or deposition non-uniformity). Random scatter means particles. A repeating reticle-position fail means a mask or stepper field defect. Read the map before you probe-debug a single die.
Yield, throughput, and multi-site
Two numbers dominate the business case. Yield is pass-dies divided by total dies—a mature logic process might sit at 85–95%, a brand-new node far lower. Throughput is driven by test time per die and by parallelism: modern cards probe many dies at once (x16, x32, or more touchdowns), so the ATE tests them simultaneously and the economics improve almost linearly with site count—until the card or power delivery can't support more parallel sites.
| Stage | Screens for | Relative cost of a miss |
|---|---|---|
| Wafer sort (this article) | Gross & structural defects, KGD | 1× (pennies) |
| Final test (packaged) | Package-induced faults, speed grade, full spec | ~10× |
| Board / system | Assembly interaction | ~100× |
| Field return | Everything missed | ~1000× |
Sort and final test are complementary, not redundant—see our deep dive on final test vs wafer test for where the boundary sits and why some tests can only run after packaging. If you want the ATPG side of the story, read how scan chains and DFT make a billion-transistor die testable in the first place.
For teams building full test programs or needing production-grade DFT and post-silicon validation support, Avecas offers hands-on semiconductor design and test engineering services that complement the fundamentals covered here.
Want to run a real sort program on an ATE simulator and read live wafer maps? CourseTron's Post-Silicon Test track walks you from probe-card basics to binning and yield analysis. Explore the courses →
Frequently Asked Questions
What is the difference between wafer test and wafer sort?
They are the same step. "Wafer sort" emphasizes the outcome—sorting dies into bins—while "wafer test" or "probe" emphasizes the electrical testing itself. All three terms refer to testing dies while still on the wafer, before dicing.
Why not just test every chip after packaging instead?
Because packaging a known-bad die wastes the entire packaging cost, which can be dollars per part and thousands of dollars in stacked/chiplet packages. Wafer sort removes bad dies for pennies before that money is spent, and it is the only way to guarantee known-good-die for advanced packaging.
What is probe card overdrive?
Overdrive is the extra vertical travel the prober chuck applies after the tips first touch the pads. It makes the tips scrub laterally through native oxide to form a low-resistance contact. Too little gives flaky contact; too much damages pads and wears tips prematurely.
Can a die that passes wafer sort still fail final test?
Yes. Final test catches faults introduced by the packaging process (bond/bump opens, thermal stress) and runs tests—full-speed, thermal, and some analog specs—that are impractical at the probe. That is exactly why both insertions exist.