Scan chain architecture

In short: Scan chain architecture reconfigures a design's existing flip-flops into one or more shift registers so that any internal state can be loaded and observed from a handful of pins, turning an opaque sequential circuit into a fully controllable, observable test structure for ATPG.

If you have ever wondered how a chip with tens of millions of flip-flops can be tested in a fraction of a second on a production tester, the answer is almost always scan. Scan design is the backbone of modern Design-for-Test (DFT), and the scan chain is its most fundamental building block. This article walks through what a scan chain actually is, how flops get stitched together, how scan-in and scan-out work, why we split a design into many chains, and how we balance them for optimal test time.

Why sequential logic is hard to test

A combinational circuit is easy to test: apply inputs, read outputs, done. A sequential circuit is not, because its behavior depends on the values stored in its flip-flops, and those values are buried deep inside the netlist. To test a fault behind a 40-deep pipeline, you would need a carefully crafted sequence of dozens of clock cycles just to drive the right state in and then propagate the effect out. Automatic test pattern generation (ATPG) for sequential logic quickly becomes computationally intractable above a few thousand flops.

Scan solves this by making every flip-flop directly controllable (we can set its value) and observable (we can read its value). Once that is true, the ATPG tool can treat the entire design as if it were a giant combinational block sitting between pseudo-inputs (scan flop outputs) and pseudo-outputs (scan flop inputs), and apply mature combinational ATPG algorithms that scale well.

From D flip-flop to scan flop

The trick is to replace each ordinary D flip-flop with a scan flip-flop — a flop fed by a 2-to-1 multiplexer. A control signal called scan-enable (SE) selects the source:

• SE = 0 (functional / capture mode): the flop captures the normal data input D, exactly like the original design.
• SE = 1 (shift mode): the flop instead captures SI, the scan input, which is wired to the output Q of the previous flop in the chain.

Wire the Q of flop 1 to the SI of flop 2, flop 2's Q to flop 3's SI, and so on, and you have built a shift register out of logic that already existed. This cell is the muxed-D scan flop, by far the most common style. Synopsys DFT Compiler, Cadence Genus/Modus, and Siemens Tessent all insert these automatically during scan insertion.

Scan-in, shift, capture, scan-out

A scan test proceeds as a repeating four-phase cycle driven entirely from the tester:

1. Shift-in: Assert SE=1 and pulse the scan clock N times (N = chain length). The test stimulus is shifted in serially through the scan-in (SI) pin, one bit per cycle, until every flop holds its intended value.
2. Capture: Deassert SE=0 for one (or a few) functional clock pulses. The combinational logic reacts to the loaded state and its response is captured back into the same flops.
3. Shift-out: Assert SE=1 again and shift the captured response out through scan-out (SO), where the tester compares it bit-by-bit against the expected signature. Cleverly, the shift-out of pattern k overlaps with the shift-in of pattern k+1, so no cycles are wasted.

Key fact: Test time is dominated by shifting, not capturing. For a chain of length N and P patterns, the cycle count is roughly (N+1) × (P+1) + P. Shaving chain length is therefore the single biggest lever on tester cost.

Why one chain is never enough: multiple scan chains

Imagine a 2-million-flop SoC stitched into a single chain. Every pattern would take over 2 million shift cycles. At a 50 MHz shift clock, that is 40 ms per pattern — and designs need thousands of patterns. The test would run for hours and blow the test budget completely.

The fix is to split the flops into many parallel chains, each with its own SI and SO pin (or, more often, fed from a small number of pins through on-chip compression). If we divide 2 million flops into 500 chains of 4,000 flops each, the longest chain is now 4,000 deep, cutting shift time by 500×. The number of chains is bounded by how many scan I/O pins (or compression channels) you can afford.

Balancing the chains

Here is the catch: all chains shift simultaneously with the same clock, so the total shift time equals the length of the longest chain. If you carelessly end up with chains of 4,000, 3,900, 100, and 50 flops, the 100 and 50 chains finish early and sit idle while the 4,000-flop chain keeps going. You paid for extra chains but got little benefit.

Chain balancing is the process of distributing flops as evenly as possible so every chain is close to the same length. A well-balanced design where max chain length ≈ average chain length extracts the full parallelism of the architecture.

In practice tools balance automatically, but good physical-aware stitching matters: flops are ordered along a chain to minimize routing wirelength (often using placement coordinates), and clock domains are kept on separate chains to avoid clock-skew-induced shift corruption. Multiple clock domains almost always get their own chains, and lockup latches are inserted between domains to safely bridge skew during shift.

Compression: the modern reality

Pin count caps the number of external chains, so modern designs use on-chip test compression (Synopsys DFTMAX/TestMAX, Cadence Modus, Siemens TestKompress/EDT). A decompressor fans a few input pins out to hundreds of short internal chains, and a compactor (typically an XOR-tree MISR) squeezes the responses back down. This routinely yields 50–200× shorter chains and a corresponding drop in pattern volume and test time, which is why nearly every production SoC uses it today. If you are preparing for interviews or building silicon, understanding this stack end-to-end is invaluable — training providers like ChipXpert's VLSI programs drill exactly these flows on commercial tools.

Want to insert, stitch, and debug real scan chains on industry EDA tools? CourseTron's DFT track takes you from flop replacement to compression and ATPG signoff with hands-on labs. Explore the CourseTron course catalog →

Frequently Asked Questions

What is the difference between scan-in and scan-out?

Scan-in (SI) is the serial port where test stimulus is loaded into the head of a chain; scan-out (SO) is the serial port at the tail where captured responses are read out. During shifting they operate together — pattern k shifts out of SO while pattern k+1 shifts into SI.

Why do we need the scan-enable signal?

Scan-enable (SE) selects the mux inside each scan flop. SE=1 puts the whole design into shift mode so flops form a shift register; SE=0 returns them to functional mode so the design behaves normally and captures the logic's response. It is the single global control that orchestrates the shift/capture cycle.

How long should a scan chain be?

Short enough to keep test time acceptable, balanced so all chains are near-equal, and bounded by available scan I/O or compression channels. With compression, internal chains of a few hundred flops are typical; without it, a few thousand is common. The longest chain, not the flop count, sets shift time.

Does scan insertion change functional behavior?

No. In functional mode (SE=0) the scan mux always selects the normal D input, so the design operates identically to the pre-scan netlist. Scan only adds area (the mux and SI routing) and the test-mode behavior that is unused during normal operation.

Ready to go deeper? Continue with scan insertion in DFT and then ATPG fundamentals to see how patterns are generated for the chains you just built. For teams needing production DFT and silicon implementation, Avecas design services handle full DFT signoff.