Scan enable timing and clock-chain balancing

In short: Scan enable (SE) is a high-fanout, static-during-capture control whose own timing and the balance of the shift clock tree decide whether your scan chains shift cleanly or produce skew-induced miscompares on the ATE — so you pipeline SE, balance the shift-clock skew, and gate SE changes to a safe shift window.

Every digital designer learns that scan insertion "just stitches the flops into a shift register." The reality on silicon is subtler. The two signals that make scan work — the scan enable and the shift clock — are also the two signals most likely to cause a chip to fail test for reasons that have nothing to do with a real manufacturing defect. This article walks through why SE timing and shift-clock balancing matter, with concrete numbers and the fixes PD and DFT engineers actually apply.

What scan enable really does

In a mux-D scan flop, a 2:1 multiplexer in front of the D input selects between functional data (D) and the scan input (SI). The select line of that mux is the scan enable. When SE=1 the chain behaves as a long shift register; when SE=0 it captures functional logic. A mid-size block of 200k flops means SE drives 200,000 mux selects — one of the highest-fanout nets on the die, rivaled only by reset and the clock itself.

Because SE touches every flop, it is almost always built as a dedicated balanced buffer tree, not left to default synthesis fanout. Tools such as Synopsys DFT Compiler and Tessent (Siemens EDA) tag SE as a scan-control net so that place-and-route (Innovus, IC Compiler II) routes it on wide, shielded tracks and inserts a clock-tree-like buffer structure.

Why SE is "static during capture" — and why that is hard

During the capture window of a transition-delay (at-speed) test, SE must be a clean, settled logic 0 before the launch and capture clock edges fire. If SE is still ramping or glitching when the launch edge arrives, some flops see scan mode and some see functional mode — the captured response no longer matches the fault-free simulation, and the tester flags a miscompare. The ATPG tool (Tessent, TetraMAX/Synopsys) assumed one clean mode; the hardware gave it two.

A 1.2 ns SE skew across a block clocked at 500 MHz (2 ns period) can leave distant flops still in shift mode when the near flops have already switched to capture — a classic source of intermittent, pattern-dependent miscompares that vanish when you slow the tester down.

The hardest case is last-shift launch (also called launch-off-shift, LOS). Here the transition is launched by the final shift pulse while SE is deasserting from 1 to 0. SE must travel from 1→0 and settle across the entire block within the single clock period between the last shift edge and the capture edge. On a 500 MHz chain that is 2 ns for a net spanning millimetres of die. This is precisely why many teams prefer launch-off-capture (LOC), where SE has a full extra dead cycle to settle and need not be fast at all.

Pipelining the scan enable

When LOS is required for coverage or when SE genuinely cannot meet timing as one global net, the standard fix is to pipeline SE: register the scan-enable signal through a small chain of flops near the delivery points, so each region of the die receives a locally retimed, skew-matched copy. The pipeline flops are themselves clocked by the shift clock, so SE arrives in a known phase relationship at every leaf.

• Balance, don't rush. Pipelining converts a hard max-delay problem into a balanced-skew problem, which CTS-style engines handle well.
• Match depth per region. All leaf SE drivers should see the same number of pipeline stages so phase is uniform.
• Protect the pipeline from DFT. The SE pipeline flops must be excluded from the scan chains they control, or you create a chicken-and-egg loop.

Clock-chain balancing for shift

Shift happens at a slow, test-only clock — often 10–50 MHz — but the chain can be tens of thousands of flops long. Here the danger is the opposite of setup: it is a hold violation. If flop N sees its shift-clock edge noticeably later than flop N+1, the data launched from N can race through and corrupt N+1 before its own capture — a shift-chain hold fail. A good lockup element between clock domains absorbs exactly this skew; see our deep dive on lockup latches in scan chains for how a level-sensitive latch between domains buys half a cycle of margin.

Where the skew budget goes

Rule of thumb: budget the shift-clock skew to under 10% of the shift period and hold-fix the chain at the slowest corner; budget SE settling against the functional (at-speed) period, because LOS launches at full speed.

A practical sign-off checklist

• Define SE and the shift clock as case-analysis / test-mode signals in your SDC so STA analyses shift and capture modes separately.
• Run hold analysis on the shift path at the slow corner with the shift clock active — this is where real chains fail.
• Verify SE reaches every leaf within the LOS window if using launch-off-shift; otherwise constrain it as a multicycle/false path and confirm LOC coverage is adequate.
• Insert lockup latches at every clock-domain boundary in the chain and confirm the reorder tool respected them.
• Correlate ATE miscompares against a skew map before blaming the netlist — if slowing the shift clock makes fails disappear, you have a skew problem, not a defect.

These same balancing principles extend to compression architectures and multi-clock chains; our companion piece on at-speed transition-fault testing shows how SE and clock timing interact with launch strategy. If you need a production flow built and signed off by people who do this daily, Avecas offers silicon-proven DFT and physical-design services.

Want to master scan insertion, SE pipelining, and shift-clock sign-off hands-on with Tessent and PrimeTime? Explore the full DFT track in the CourseTron VLSI courses.

Frequently asked questions

Why does slowing the tester clock make miscompares disappear?

Slowing the shift or capture clock lengthens the window in which SE and the shift clock must settle. A skew-induced fail is a timing race; give it more time and the race resolves correctly. A true manufacturing defect does not care about clock speed, so this is the fastest way to tell the two apart.

When should I pipeline scan enable instead of just building a bigger buffer tree?

Pipeline SE when you use launch-off-shift and SE cannot meet the at-speed launch-to-capture window as a single combinational net — typically on large blocks or high-frequency designs. For launch-off-capture, SE has an extra dead cycle and a balanced buffer tree is usually enough.

Is a hold violation on the shift path the same as a functional hold violation?

Mechanically yes — data arrives too early relative to the clock edge — but it is checked in test mode at the shift clock with SE asserted, a state ordinary functional STA may not exercise. That is why you must explicitly analyse the shift configuration, and why lockup latches at domain crossings are standard practice.

Which tools tag and balance the scan-enable net automatically?

Synopsys DFT Compiler and Siemens Tessent mark SE as a scan-control net during insertion; Innovus and IC Compiler II then route it on protected tracks and can build a balanced or pipelined SE structure during clock-tree synthesis.