In short: A transition fault models a gate that switches too slowly to meet timing, and at-speed testing catches it by applying two carefully timed vectors at the functional clock rate. The two launch styles — launch-on-shift and launch-on-capture — differ in how the transition is created and trade test coverage against pattern count and over-testing.
A transition fault is a delay fault model that assumes a single node in the design is slow to make one specific logic transition — either slow-to-rise (a 0→1 that arrives late) or slow-to-fall (a 1→0 that arrives late). Unlike the classic stuck-at model, which assumes a node is permanently tied to a value, the transition fault model assumes the node eventually reaches the correct value but misses the timing window defined by the clock period.
The underlying idea is that a defect — a resistive via, a partially open contact, process variation, or crosstalk — adds enough extra delay along a path that the captured value is wrong at the clock edge. Because the error only appears when the circuit runs fast, the chip can pass a slow DC functional test and still fail in the customer's system. That is exactly the escape that at-speed testing exists to prevent.
Stuck-at patterns are applied slowly: load the scan chain, apply one vector, capture, unload. Timing is irrelevant, so a slow gate still produces the right final value and the test passes. As geometries shrank and clock frequencies climbed, delay-related defects became a dominant failure mode, and purely static tests began to let bad parts through.
At-speed testing closes that gap by requiring a launch event and a capture event separated by exactly the functional clock period (or the targeted path's rated delay). The first vector sets up an initial value; the second drives the transition; the capture edge samples the result at speed. If the slow node cannot settle in time, the captured value differs from the fault-free simulation and the pattern detects the fault.
Each node carries two transition faults. A slow-to-rise fault requires a pattern that forces the node from 0 to 1 and then sensitizes a path so the late-arriving rising edge is captured. A slow-to-fall fault is the mirror case: the node is driven 1 to 0 and the falling edge must be observed. Full transition-fault coverage means detecting both polarities on every testable node, which roughly doubles the fault list relative to a single-polarity view.
Two timing conventions decide how the expected value is computed:
These are the two dominant ways to generate the launch transition in a standard scan (muxed-flop) design, and the choice shapes everything downstream.
In LOS, the scan chain is shifted in, and the last shift pulse itself launches the transition at the functional speed, followed immediately by a fast capture pulse. Because the launch comes from a shift, the scan-enable signal must switch from shift mode to capture mode within one fast clock cycle — a tight, timing-critical requirement on the scan-enable network. LOS generally gives higher fault coverage with fewer patterns because the launch value is directly controllable through the scan chain, so the ATPG engine has more freedom.
In LOC, the chain is shifted in, scan-enable is de-asserted (giving it a full cycle to settle), then the first capture pulse launches the transition through the combinational logic and the second capture pulse samples it. Scan-enable is not timing-critical, which simplifies physical design and clock-domain handling. The cost is that the launch value is now the functional response of the logic, not a directly loaded value, so some faults become hard or impossible to launch, lowering coverage and raising pattern count.
A practical summary of the trade-off:
In a real DFT flow, transition-fault ATPG runs after stuck-at ATPG, usually reusing the same scan architecture. A few practices make the test trustworthy:
Coverage is reported as transition-fault coverage, and gaps are usually launch problems (for LOC) or untestable paths that are then handed to path-delay ATPG, which targets specific critical timing paths rather than individual nodes.
Commercial ATPG engines — Synopsys TestMAX (formerly TetraMAX), Siemens EDA Tessent, and Cadence Modus — all support transition fault generation with selectable LOS or LOC launch, SDF-based timing-aware modes, OCC-driven at-speed clocking, and power-aware pattern compaction. Engineers typically generate stuck-at and transition patterns in one campaign, apply on-chip compression (scan compression) to control pattern volume, and sign off on a combined coverage target. The same tools report which faults are AN (ATPG untestable) versus detected, which guides whether to add test points or accept the gap.
Real projects and industry tool flows, with certification.
Explore CourseTron Courses →A transition fault targets a slow transition at a single node and assumes the whole extra delay is lumped there, so one pattern pair per polarity per node suffices. A path-delay fault targets the cumulative delay along a specific, usually critical, path and is used to catch small distributed delays that no single node would flag. Transition faults give broad coverage cheaply; path-delay faults give precise coverage on timing-critical paths.
LOS launches the transition on the last shift pulse, so the scan-enable signal has to switch from shift to capture within one at-speed cycle. That makes scan-enable a timing-critical, often pipelined net that must close timing like a functional signal. LOC de-asserts scan-enable a full cycle before capture, so it is not timing-critical, which is why LOC is frequently chosen even though its coverage is lower.
Over-testing is failing a good die because a test pattern exercised a path at a speed the chip never actually uses in its functional mode — for example a false path or a multicycle path treated as single-cycle. It hurts yield without improving quality. It is avoided by giving the ATPG tool accurate timing information and masking false and multicycle paths. LOC over-tests less than LOS because its launch comes from functional logic behavior.
Because the fault is about a change over time, not a static value. You need one vector to establish the starting logic value and a second, at-speed vector to create the transition and sensitize a path to a capture point. Only by comparing the captured value to the fault-free timing simulation can you tell whether the node switched within the clock period.
Related: a related topic · the VLSI Glossary · all courses.