In short: IEEE 1500 standardizes a test wrapper around each embedded core so a large SoC can be tested one block at a time, using a serial WIR-controlled register and parallel ports with inward- and outward-facing modes that isolate the core internally and verify the logic around it.
Modern SoCs stitch together dozens of pre-designed cores: CPU clusters, DDR controllers, SerDes, large SRAM-backed accelerators, and third-party IP delivered as hardened GDSII. You cannot practically flatten all of that into one monolithic scan chain and generate patterns for the whole thing at once — ATPG runtime and pattern count explode, and the IP vendor rarely ships a netlist you can re-synthesize. IEEE 1500 solves this by placing a standardized test wrapper around each core, so each block becomes a self-contained, independently testable unit. This is the structural backbone of hierarchical DFT.
Why wrap a core at all?
The wrapper exists to answer two separate questions. First, is the core itself good? You want to drive patterns into the core while shielding it from whatever noise sits on the chip-level interconnect. Second, is the logic around the core — the interconnect and glue — good? You want to control and observe the core's boundary without needing the core's internals. A single ring of wrapper cells, reconfigured by mode, serves both purposes. This mirrors the idea behind IEEE 1149.1 (JTAG) boundary scan at the board level, but applied one hierarchy down, at the core boundary inside the die.
IEEE 1500 (ratified 2005, formally IEEE Std 1500-2005) defines the wrapper architecture and a control language (CTL) — not a bus protocol. Unlike 1149.1, it deliberately leaves the test access mechanism (TAM) to the SoC integrator, because a DDR core and a tiny GPIO core need very different test bandwidth.
Anatomy: WIR, WBR, WBY and the ports
Every 1500 wrapper is built from a small, fixed set of registers controlled by the Wrapper Serial Port (WSP):
- WIR (Wrapper Instruction Register) — the brain. Like JTAG's IR, you shift an instruction in serially to select the active mode (e.g.
WS_BYPASS,WS_EXTEST,WS_INTEST). The decoded instruction gates every other register. - WBR (Wrapper Boundary Register) — the ring of wrapper cells on the core's functional I/O. These provide the control/observe points.
- WBY (Wrapper Bypass Register) — a single-bit shortcut so the serial chain skips an inactive core, exactly like JTAG BYPASS.
Two port styles exist. The mandatory serial interface — WSI (in), WSO (out), and the WSC control group (WRCK, WRSTN, SelectWIR, ShiftWR, CaptureWR, UpdateWR) — is always present and is how instructions are loaded. The optional parallel interface (WPI/WPO, several bits wide) is what delivers real test bandwidth: a 32-bit WPP lets you push patterns ~32x faster than the single-bit serial path, which matters when a core needs 50,000 scan patterns.
Inward-facing vs outward-facing: the two modes that matter
This is the concept interviewers probe hardest, and the one the WBR cell is designed around. Each wrapper boundary cell can be configured to drive and observe in either direction:
| Mode (instruction) | Facing | What it tests | WBR drives / observes |
|---|---|---|---|
WS_INTEST | Inward | The core's own internal logic in isolation | Input cells drive the core; output cells observe the core |
WS_EXTEST | Outward | Interconnect/glue logic between cores | Output cells drive the chip net; input cells observe the neighbor |
WS_BYPASS | — | Nothing; shortens the serial chain | WBY only |
Think of a core as a room with a ring of switchable sockets. In INTEST (inward-facing), the sockets point into the room: the input cells inject controlled stimulus so ATPG can target the core's internals, while output cells capture responses — the surrounding chip is held constant and invisible. In EXTEST (outward-facing), the sockets point outward: output cells launch transitions onto the chip-level wires so you can verify the routing, buffering, and any "kill logic" sitting between this core and its neighbor. Because the ring isolates the core either way, the vendor can hand you compressed patterns for INTEST without ever exposing how the interconnect is wired.
A practical consequence: a core that is INTEST-isolated can be tested concurrently with its neighbors if the TAM gives each enough bandwidth. Tools like Synopsys TestMAX (formerly DFTMAX/TetraMAX), Siemens Tessent, and Cadence Modus all build 1500-style wrappers and then schedule cores in parallel to cut total tester time — often the single biggest lever on cost-of-test.
A worked walk-through of one test session
Say we have a hardened crypto accelerator core. To run its internal scan test:
- Assert
SelectWIR, shift theWS_INTESTopcode into the WIR via WSI, pulseUpdateWR. The core is now inward-facing and isolated. - Configure the WBR input cells to source the core's scan-in from the parallel WPI; load 32 scan chains in parallel.
- Shift in a pattern, pulse the functional clock for capture, shift responses out on WPO while shifting the next pattern in — standard scan, just funneled through the wrapper.
- To then check the wiring to the adjacent DMA core, reload the WIR with
WS_EXTESTand let the output cells launch edges onto the shared bus.
The animation below shows a single test bit propagating through the serial chain and being captured — the mechanical heart of every shift/capture/update cycle.
Where it fits in the DFT flow
IEEE 1500 rarely lives alone. In a real flow the serial WSP is usually reachable through an IEEE 1149.1 TAP or, increasingly, IEEE 1687 (IJTAG) which models the wrapper as a network of instruments. The wrapper's parallel port connects to a TAM that could be a dedicated test bus or reuse the functional bus. If you're building toward a tapeout, pairing 1500 wrappers with an in-house or commercial DFT flow is exactly the kind of work design-service teams such as Avecas VLSI design services handle end-to-end. For the full picture of how wrappers, TAMs, and test scheduling combine, see our deeper piece on test access mechanisms and TAM scheduling.
Want to actually build a 1500 wrapper, write the CTL, and run INTEST/EXTEST on a real core in Tessent and TestMAX? Our CourseTron DFT course takes you from boundary-scan fundamentals to hierarchical pattern retargeting with hands-on labs.
Frequently asked questions
How is IEEE 1500 different from IEEE 1149.1 (JTAG)?
1149.1 is a board-level standard that tests connections between packaged chips through a fixed 4/5-pin TAP. 1500 is a core-level standard inside a single die, with a serial and an optional wide parallel port, and it deliberately leaves the access mechanism to the integrator so bandwidth can be scaled per core.
What exactly does the WIR do?
The WIR holds the active instruction. You shift an opcode in serially, pulse UpdateWR, and the decoded value selects the wrapper mode (INTEST, EXTEST, BYPASS, etc.) and routes the data registers accordingly. Nothing else in the wrapper changes mode without going through the WIR.
Why do we need both inward- and outward-facing modes?
They test different things. Inward-facing (INTEST) isolates and tests the core's own logic; outward-facing (EXTEST) tests the interconnect and glue logic between cores. One ring of WBR cells, reconfigured by the WIR, covers both, which keeps wrapper area low.
Does the wrapper add area and timing overhead?
Yes — each functional I/O gets a wrapper cell (a few gates plus a mux in the functional path), so expect low-single-digit percent area and a small added delay on wrapped signals. Shared/merged wrapper cells and reusing existing scan flops are the usual ways to keep that overhead down.