In short: Hierarchical DFT wraps each core with an IEEE 1500 test shell so patterns are generated once per block and retargeted through the chip-level interface, turning an intractable flat-ATPG problem on a 500-million-gate SoC into a set of small, parallel, reusable divide-and-conquer jobs.
When a design crosses a few tens of millions of gates, flat test generation stops scaling. ATPG runtime grows super-linearly, pattern files balloon into the tens of gigabytes, and a single RTL change forces you to regenerate everything. Hierarchical DFT is the industry answer: test each core in isolation, lock that result behind a standard wrapper, and stitch the blocks together at the top without ever re-opening them. This article walks through core wrapping with IEEE 1500, pattern retargeting, and why the divide-and-conquer model has become the default on large SoCs.
Why flat test generation breaks down
Consider a 300-million-gate SoC built from a CPU cluster, a GPU, several memory controllers and a dozen peripheral IPs. A flat scan-ATPG run must hold the entire gate-level netlist and its fault list in memory at once. In practice this means 200–400 GB of RAM, multi-day runtimes, and a pattern set so large that tester memory (often 512 Mb–2 Gb per pin channel) cannot hold it. Worse, the model is fragile: change one IP and the whole run is invalidated.
Hierarchical DFT replaces one giant problem with many small ones. Each core — say an 8-million-gate CPU — is tested on its own. Tools like Synopsys TestMAX (formerly TetraMAX), Siemens Tessent, and Cadence Modus generate compact, high-coverage patterns for that block in minutes, and those patterns are reused across every instance and every parent chip.
Scale example: Generating patterns for twelve 8M-gate cores in parallel typically completes in under an hour and reaches 98–99% stuck-at coverage, versus 2–4 days for a single flat run on the assembled 300M-gate netlist — with a 5–10× smaller total pattern volume thanks to compression and reuse.
Core wrapping with IEEE 1500
The enabling standard is IEEE 1500, the Standard Testability Method for Embedded Core-Based ICs. It defines a test wrapper — a thin shell of boundary cells around a core — plus a standardized access mechanism. The wrapper has three modes that matter:
- INTEST — the wrapper isolates the core internals so patterns target logic inside the core.
- EXTEST — the wrapper tests the interconnect and glue logic between cores at the parent level.
- Functional/bypass — the wrapper becomes transparent during mission mode.
Access is through the Wrapper Serial Port (WSP): a WSI/WSO serial pair plus a Wrapper Instruction Register (WIR) and the Wrapper Boundary Register (WBR). This is deliberately analogous to IEEE 1149.1 (JTAG) and IEEE 1687 (IJTAG) — the WIR is loaded like a TAP instruction, then wrapper cells shift like a boundary-scan chain. The payoff: a core-level test is a self-contained, portable object. Whoever integrates the core only needs the WSP pins, not its internals.
Pattern retargeting: generate once, reuse everywhere
The second pillar is pattern retargeting. Patterns are generated at the core level, where the ATPG tool sees a small, controllable netlist. During integration those same patterns are mapped — retargeted — to the chip-level pins. The tool knows the path from each top-level pin, through the IJTAG/1500 network, to the core's WSP, and rewrites the shift/capture protocol accordingly. No re-ATPG is performed; coverage is preserved by construction.
This is where a block that appears four times on a die costs you one ATPG run, not four. The core's compact pattern set is retargeted to each instance, and the tester applies them through a shared or broadcast network. Tessent calls this flow "retargeting"; TestMAX Hierarchical and Modus implement the same concept against the 1500/1687 access hardware.
Divide-and-conquer integration
At the top level the SoC is assembled from wrapped, pre-verified cores. Chip-level DFT then only has to deal with two things: the interconnect between cores (EXTEST patterns exercising the wrapper boundary cells and top glue logic) and the access network that routes data to each WSP. The heavy internal-fault work is already done and signed off per block.
This also parallelizes the schedule. Block teams close their DFT independently, in their own timezones and runs, while the SoC integration team works the network. A late RTL ECO in one IP triggers re-ATPG for that one core only — a few minutes — instead of a multi-day flat rerun. Teams building large designs at firms like Avecas VLSI design services rely on exactly this isolation to hit tapeout dates.
| Aspect | Flat ATPG | Hierarchical DFT |
|---|---|---|
| Memory footprint | Whole chip (200–400 GB) | One core at a time |
| Runtime | Days, serial | Hours, parallel |
| Pattern reuse | None | Per-instance via retargeting |
| ECO impact | Full rerun | Affected core only |
| Standard interface | Ad hoc | IEEE 1500 WSP |
Rule of thumb: If any single hard macro or IP exceeds ~5M gates, or the chip has >3 instances of the same block, hierarchical DFT almost always wins on both runtime and tester-memory budget.
Practical gotchas
- Wrapper cell placement: shared/dedicated wrapper cells affect timing and area. Dedicated cells are safest but add flops on every core port.
- Clock domains at the boundary: EXTEST across cores on different clocks needs careful at-speed timing and the right launch/capture setup.
- Network bandwidth: a single serial IJTAG path can bottleneck retargeted shift time; many designs add parallel scan access (e.g. Tessent's Streaming Scan Network or TestMAX's broadcast groups).
- Low-power domains: wrappers must respect UPF power states so you do not test a powered-down core.
Getting these right is the difference between a clean hierarchical flow and one that silently loses coverage. If you are building the full insertion flow, start from our DFT insertion flow guide, and pair it with the scan compression walkthrough to understand how per-core patterns stay tester-friendly.
Want to run a real IEEE 1500 wrapping and retargeting flow in Tessent and TestMAX? The hands-on DFT track on CourseTron courses takes you from scan insertion to a fully hierarchical, retargeted SoC. For corporate and university cohorts, see ChipXpert VLSI training.
Frequently asked questions
Is IEEE 1500 the same as JTAG?
No. JTAG (IEEE 1149.1) is a chip-level boundary-scan and access standard with a single TAP. IEEE 1500 is a core-level wrapper standard. They are complementary: JTAG/IJTAG (1687) usually provides the top-level access that reaches each 1500 wrapper's serial port.
Does retargeting reduce fault coverage?
No. Retargeting only changes how patterns are delivered — the serial protocol from chip pins to the core WSP. The stimulus and expected responses are identical to the core-level run, so stuck-at and transition coverage are preserved by construction.
When is flat ATPG still the right choice?
For small designs (under ~5–10M gates), a single flat run is simpler, avoids wrapper area/timing overhead, and finishes quickly. Hierarchy pays off only when scale, repeated instances, or parallel team schedules demand it.
Which tools support hierarchical DFT?
Siemens Tessent (TestKompress + hierarchical retargeting), Synopsys TestMAX Hierarchical, and Cadence Modus all implement IEEE 1500 wrapping and pattern retargeting against 1687/IJTAG access networks.