In short: Memory redundancy adds spare rows, columns (and sometimes spare blocks) to an SRAM or DRAM so that a few defective cells can be swapped out at test time, and built-in self-repair (BISR) uses the on-chip BIST engine plus programmable fuses to make that swap permanent — turning a failing die into a shippable one and lifting yield by meaningful percentage points.
On an advanced SoC, embedded memory can occupy more than half the silicon area and contains billions of the smallest, most aggressively-sized transistors on the chip. Statistically, that makes memory the single largest contributor to random defect yield loss. Memory redundancy and repair is the discipline of designing deliberate spare capacity into each array and then using test hardware to route around whatever happens to be broken. This article walks through the physical structures, the repair algorithms, how fuses make a repair stick, and how the yield math actually works — the kind of depth a DFT interviewer expects.
Why memories fail where logic survives
A manufacturing defect — a particle, a shorted bitline, a weak contact — that lands in random logic may corrupt one gate. The same defect in a memory lands in a sea of identical cells, and because memory bitcells are drawn at the minimum design rules the foundry allows, the array is where marginal processing shows up first. Defects cluster into recognisable fault types: single-cell stuck-at, a stuck bitline (whole column fails), a stuck wordline (whole row fails), bridging between adjacent cells, and address-decoder faults. The key insight behind redundancy is that most of these failures are localised to a row or a column, so a spare row or column can absorb them entirely.
A 7nm SoC may integrate several thousand individual SRAM instances. If even 0.5% of unrepaired dies fail solely because of a single bad memory cell, repair that recovers them directly converts to margin.
The physical structures: spare rows, columns and blocks
A repairable memory is laid out with extra, normally-unused redundant elements:
- Spare rows (redundant wordlines) — replace a failing row. A row with one bad cell is swapped out entirely; the spare row's address decoder is reprogrammed to answer to the failing row's address.
- Spare columns (redundant bitlines / IO) — replace a failing column or a stuck bit position across all rows. Column repair is usually done at the granularity of an IO (a group of columns feeding one data bit) because the column mux already groups them.
- Spare blocks / banks — coarse-grained repair used in large DRAM where entire sub-arrays can be substituted.
BISR: how the chip repairs itself
Modern designs do not probe each cell externally — that is far too slow at billions of cells. Instead the Memory BIST (MBIST) engine, generated by tools such as Siemens Tessent MemoryBIST, Synopsys STAR Memory System, or Cadence memory test IP, applies March algorithms (March C-, March SS, etc.) at speed and records which addresses fail. A companion Built-In Redundancy Analysis (BIRA) block then solves a small combinatorial problem: given the set of failing addresses and the available spares (say 2 spare rows + 1 spare column), find an allocation that covers every failure. This is the classic must-repair / most-repair analysis. BISR is the full loop — BIST detects, BIRA computes the solution, and the repair registers are loaded so the array routes around the faults.
There are two timing models. Soft repair runs the analysis every power-on and loads the solution into volatile repair registers — cheap but repeats each boot. Hard repair blows fuses once, so the solution is permanent and non-volatile. Many SoCs do both: hard-repair the solid defects at wafer sort, soft-repair any later marginal failures at every boot.
Fuse programming: making a repair permanent
The repair solution is a handful of bits — "spare row 0 now answers to address 0x3A1", "spare IO 1 replaces data bit 5". Those bits are stored in non-volatile fuses, typically eFuse (an electrically-blown poly or metal link programmed with an on-chip charge pump) or antifuse (an oxide that is intentionally ruptured to form a connection). At boot, a fuse controller reads the fuse array, decompresses the repair chains, and shifts them into the distributed repair registers next to each memory. Because fuse bits are precious, designs often share one central fuse box across many memories and use a serialized, compressed repair-chain format rather than dedicating fuses per instance.
eFuse programming is one-time and irreversible. A mistake in the repair signature can brick a good die, which is why BIRA correctness and fuse integrity (parity/ECC on the fuse array itself) are taken very seriously in silicon bring-up.
The yield math — why this pays for itself
Redundancy costs area (the spares and the BISR/fuse logic, often 2–5% of the memory). The payback is yield. A simplified view: if a memory has an unrepaired yield Ymem, and a spare row can fix any die whose only defect is a single row failure, then the repaired yield is Ymem plus the probability mass of exactly-repairable dies. In practice foundries model this with Poisson defect statistics and report repair effectiveness — the fraction of failing dies that redundancy recovers.
| Scenario | Typical effect | Notes |
|---|---|---|
| No redundancy | Baseline, every cell defect kills the die | Unviable for large arrays at advanced nodes |
| Spare rows only | Recovers row-localised faults | Cheapest; good for stuck-wordline defects |
| Rows + columns (2D) | Highest recovery, handles bitline + cell faults | Needs smarter BIRA (must-repair/most-repair) |
| Rows + columns + ECC | Repairs hard defects, ECC masks soft/residual | Common in HBM/DRAM and large caches |
Redundancy and ECC are complementary, not competing: repair removes hard manufacturing defects so that ECC's correction budget is reserved for soft errors (particle strikes, retention) in the field. Spending the ECC budget covering permanent defects would be wasteful and risky.
Where this fits in the DFT flow
Memory repair is inseparable from memory test — the same MBIST controller both detects faults and feeds BIRA. If you are coming to this fresh, start with our companion on MBIST and memory BIST, then look at how repair interacts with scan and compression in scan compression and EDT. Teams that want hands-on exposure to Tessent and STAR flows can see the CourseTron DFT course catalogue, and if you need production silicon test or repair-aware RTL built for a real tapeout, the design-services team at Avecas handles end-to-end DFT insertion.
Ready to master MBIST, BIRA and fuse-based repair with real tool flows? Join the CourseTron DFT & Memory Test course and build a repairable SRAM from spec to fuse map.
FAQ
What is the difference between BISR and MBIST?
MBIST is the engine that tests a memory at speed using March algorithms and reports failing addresses. BISR is the larger self-repair loop that adds redundancy analysis (BIRA) and fuse/repair-register programming on top of MBIST so the chip can route around the faults MBIST found.
What is the difference between soft repair and hard repair?
Soft repair recomputes and reloads the repair solution into volatile registers at every power-on, so it is reusable but non-permanent. Hard repair blows fuses once at test time, making the repair permanent and automatically restored on every subsequent boot.
Why use both redundancy and ECC in the same memory?
Redundancy fixes permanent manufacturing defects (bad cells, rows, columns), while ECC corrects transient soft errors during operation. Using repair for hard defects keeps the limited ECC correction capacity free to handle field errors, which is the safer and more area-efficient division of labour.
How many spares does a typical SRAM carry?
It is design-specific, but small embedded SRAMs commonly carry one or two spare rows and one or two spare IOs (column groups). Large DRAM arrays carry far more, including spare rows, columns and whole sub-blocks, because their defect exposure is much higher.