Scan compression (EDT)

In short: Scan compression (embedded deterministic test, or EDT) inserts an on-chip decompressor that fans a few scan-input pins out to hundreds of internal scan chains, and a compactor that folds the responses back to a few outputs — shrinking test-data volume and test time by 10x–200x with no loss of ATPG coverage.

If you have ever stared at an ATE time estimate and watched it balloon past a minute of test per die, you already understand why scan compression exists. Modern SoCs can hold tens of millions of scan cells. Shifting patterns in and out of those cells one bit at a time, through a handful of chip pins, is the single largest consumer of tester time and tester memory in manufacturing test. Scan compression attacks both problems at once. This article explains how the decompressor and compactor actually work, why they do not hurt coverage, and what the trade-offs look like in a real flow.

Why uncompressed scan does not scale

In a plain scan design, every scan flop is stitched into a small number of long shift registers. Suppose a block has 2,000,000 scan cells and you can afford, say, 8 scan-in/scan-out pin pairs. That gives 8 chains of roughly 250,000 cells each. The shift depth per pattern is therefore 250,000 cycles just to load, plus the same to unload. If ATPG produces 40,000 patterns and the shift clock runs at 50 MHz, the arithmetic is brutal:

Test time ≈ patterns × chain-length × 2 ÷ shift-frequency. With 40,000 patterns and 250,000-deep chains, that is roughly 40,000 × 500,000 ÷ 50e6 ≈ 400 seconds per die — commercially impossible.

Test-data volume scales the same way: each pattern must store a care/don't-care bit for every cell, so the pattern file and the tester vector memory both explode. The root cause is the mismatch between a few package pins and millions of internal cells. Compression breaks that bottleneck by changing the ratio of external chains to internal chains.

The core idea: decompressor in, compactor out

EDT wraps the scan logic with two pieces of combinational-plus-sequential hardware:

• Decompressor — sits between the external scan-in pins and the internal scan chains. A small number of external channels (say 8) drive a much larger number of short internal chains (say 400). The decompressor expands each shift cycle's input bits into the wider internal load.
• Compactor — sits between the internal chains and the external scan-out pins. It folds the 400 chain responses back down to 8 (or fewer) observe channels every cycle.

Because the 2,000,000 cells are now split across 400 chains instead of 8, each chain is only about 5,000 cells deep. Shift depth drops from 250,000 to 5,000 — a 50x reduction in both time and volume, before counting any pattern-count effects.

Inside the decompressor

The decompressor is not a memory — it is a small sequential network, typically a ring generator (a modified LFSR) feeding a phase shifter made of XOR gates. Each shift cycle, the ring absorbs the handful of external input bits and spreads a different linear combination of its state to every internal chain. The result is that the tester delivers only the compressed stimulus — far fewer bits than the internal chains consume — and the hardware reconstructs the full load on chip.

The clever part is how ATPG cooperates. A deterministic test cube contains mostly don't-care bits (often 95-99% X). The tool solves a system of linear equations so that the few specified bits land in the right scan cells after decompression, while the X positions take whatever the linear network produces. Because specified bits are sparse, a narrow input is enough to satisfy them. This is why EDT is called "embedded deterministic test" — the patterns are still exact, targeted ATPG patterns, not pseudo-random BIST vectors.

Compression ratio is fundamentally limited by the maximum number of specified (care) bits in any single pattern. If a pattern needs 300 care bits and you feed 8 channels over 5,000 cycles, you have 40,000 free variables — plenty. Patterns that are too densely specified force the tool to lower the effective ratio.

Inside the compactor

On the output side, 400 chains cannot each get their own pin, so an XOR-based combinational compactor (often a spatial compactor with multiple-input signature-free XOR trees) merges many chains onto each output every cycle. The danger is aliasing and masking: if two chains carry opposing error values into the same XOR, a real fault effect can cancel and go unobserved, and an unknown value (X) from an uninitialized latch or non-scan memory can corrupt an entire output cycle.

Commercial compactors solve this with X-masking logic — a programmable gate that blocks offending chains for specific cycles — and by using XOR topologies that guarantee each chain reaches at least two outputs, so a single error is never fully cancelled. The ATPG engine models all of this; it will not credit a fault as detected unless the fault effect survives compaction to an observe pin.

What you actually save

Real projects commonly report 20x-100x on data volume and test time; aggressive configurations with 2D compaction push higher. The tooling is mature: Siemens EDA's TestKompress (EDT), Synopsys DFTMAX and DFTMAX Ultra, and Cadence Modus all implement the decompressor/compactor pair with X-tolerant compaction and integrate directly with their ATPG engines.

Practical gotchas

• X-sources must be controlled. Uninitialized memories, bus contention, and clock-domain mismatches inject Xs that eat into compaction. Bound them with X-bounding logic or masking, or coverage collapses.
• Balance your chains. Hugely unequal chain lengths waste shift cycles because every pattern runs to the longest chain. Let the DFT tool balance partitions.
• Pattern density caps the ratio. Launch-off-capture transition patterns and high-care-bit stuck-at patterns limit how aggressive you can be. If you understand how ATPG builds those cubes (see our ATPG explained primer), the ratio choice becomes obvious.
• Bypass mode matters. Keep an uncompressed bypass path for debug and for diagnosing which chain and position a failure maps to; our scan chain architecture walkthrough covers stitching and reorder rules.

Teams designing a full DFT sign-off flow — compression, MBIST, boundary scan, and diagnosis — often lean on specialist design-services help; Avecas offers exactly this kind of VLSI DFT and physical-design engagement for tape-out-ready chips.

Want to run a real EDT setup, tune the compression ratio, and read a compactor diagnosis report by hand? Our DFT track on CourseTron courses takes you from scan insertion to signed-off compressed ATPG on an industry tool flow.

Frequently asked questions

Does scan compression reduce fault coverage?

No, when configured correctly. EDT uses deterministic ATPG patterns, not random vectors, and the ATPG engine models the decompressor and compactor so it only credits faults whose effects survive to an observe pin. Coverage is essentially identical to uncompressed scan; you may see a tiny pattern-count increase to work around X-masking.

What is the difference between EDT and logic BIST?

Logic BIST generates pseudo-random patterns on-chip and compares a signature — great for in-field self-test but weak on hard-to-detect faults without test points. EDT ships compressed deterministic patterns from the tester, keeping full targeted coverage while still shrinking data and time. Many designs use both.

What limits the maximum compression ratio?

The most densely specified pattern. Compression works because test cubes are mostly don't-cares; the decompressor must still satisfy every care bit through linear equations. When a pattern's care-bit count approaches the available free variables (channels times shift depth), the effective ratio drops.

Why do unknown (X) values hurt compression so much?

A single X entering an XOR compactor can corrupt the whole output cycle, hiding real fault effects on other chains merged into that output. That is why X-bounding and programmable X-masking logic are essential parts of a production compactor.