In short: In scan compression, a spatial XOR compactor squeezes hundreds of internal scan chains down to a handful of output pins, while a MISR (Multiple-Input Signature Register) folds every captured response cycle into one final signature — trading a huge data-volume reduction for a small, bounded risk of aliasing that good design keeps below the escape budget.
Modern SoCs can hold tens of millions of scan flops spread across hundreds or thousands of internal scan chains. Shifting every captured bit off-chip through a dozen scan-out pins would take astronomically long and blow the ATE memory budget. Compaction is the answer: it reduces the output response volume so that only a compressed footprint of each test ever reaches the tester. This article explains the two dominant response-compaction styles — combinational XOR compactors (spatial) and the MISR (temporal/time compaction) — the math of signature analysis, and the failure mode engineers worry about most: aliasing.
Why compact the response at all?
Scan compression (Synopsys DFTMAX/TestMAX, Cadence Modus, Siemens Tessent TestKompress) has two halves. On the input side, a decompressor fans a few scan-in channels out to many short internal chains. On the output side, a compactor does the reverse: it merges the many short chains back down to a few scan-out channels. A typical compression ratio of 100x means 500 internal chains driven from and observed through roughly 5 pins. Without output compaction the decompressor alone would be useless — you would still be pin-limited on the way out.
A 50-million-flop design at 100x compression can cut ATE test-data volume and test time by roughly two orders of magnitude, often turning a 40 ms pattern set into well under 1 ms — directly lowering cost-per-second on the tester.
Spatial compaction: the XOR (parity) compactor
A combinational compactor is a tree of XOR gates. Each scan-out pin is the XOR (parity) of a chosen subset of internal chains, evaluated every shift cycle. Because XOR is linear over GF(2), the compactor simply reports whether the number of 1s among the observed chains is even or odd at each position.
The catch is unknown (X) values. An uninitialized RAM, a non-scan flop, or a bus contention injects an X into a chain. Because X ⊕ anything = X, a single X corrupts the parity of every output it feeds, masking real faults on sibling chains. Industrial compactors therefore pair the XOR network with X-handling logic — see our companion piece on X-masking in DFT — so X-sources can be blocked before they reach the compactor. Advanced compactors (e.g. Tessent's "X-tolerant" and Synopsys's X-blocking schemes) use selectable gating per shift cycle so observability is preserved on clean chains.
Temporal compaction: the MISR and signature analysis
A MISR is a Linear Feedback Shift Register with one XOR injection point per stage. Instead of streaming each response cycle to the tester, the MISR mixes incoming response data into its state every clock, so after N cycles a 32-bit MISR has compressed an N×m response matrix into a single 32-bit signature. The tester compares only that final signature against the fault-free golden value computed in simulation.
Formally the MISR evolves its state polynomial by multiplying by x modulo a fixed characteristic polynomial and adding the new input vector, all over GF(2). A primitive characteristic polynomial of degree k gives the register a maximal cycle length of 2k−1, which maximizes state mixing and minimizes correlation between error patterns.
A 32-bit MISR aliases only when the cumulative error pattern lands exactly on a multiple of its characteristic polynomial. For random error patterns the aliasing probability is approximately 2−32 ≈ 2.3×10−10 — negligible against typical DPM targets.
Aliasing: when a bad chip passes
Aliasing (also called error masking) is the event where a faulty response produces the same signature as the good response, so the tester declares PASS on a defective die. Two mechanisms dominate:
- Spatial aliasing in an XOR compactor: an even number of errors on chains feeding the same parity output cancel. Two simultaneous captured errors XORing to 0 vanish at that pin.
- Temporal aliasing in a MISR: the error polynomial is divisible by the MISR's characteristic polynomial, so the residue is zero and the signature is unchanged.
The headline result from signature-analysis theory: for a k-bit MISR with an equiprobable error model, the aliasing probability converges to 2−k as the response length grows, independent of pattern count. This is why 16-bit signatures (≈1.5×10−5) are considered risky for high-reliability parts while 32-bit is the industry default.
| Compaction style | Domain | Main risk | Typical mitigation |
|---|---|---|---|
| XOR / parity tree | Spatial (per cycle) | X-masking, even-error cancel | X-tolerant gating, multiple output taps |
| MISR | Temporal (over N cycles) | Polynomial aliasing | Primitive 32-bit polynomial |
| Combined (convolutional) | Both | Residual X leakage | Per-shift X-masking + MISR |
Practical design guidance
In a real flow, three choices keep aliasing in budget. First, size the MISR to at least 32 bits for production silicon. Second, use a primitive polynomial so the LFSR reaches maximal length — the EDA tool's default (e.g. Tessent's standard MISR polynomials) is already primitive; do not hand-edit it. Third, fence off X-sources before compaction, because uncontrolled Xs do far more coverage damage than theoretical aliasing. If a pattern set shows an unexpected coverage drop after turning compression on, the usual culprit is an un-masked X reaching the compactor, not aliasing itself. Teams building silicon with firms like Avecas VLSI design services routinely audit the X-source list before signing off the compressed pattern set.
For verification, always diff the compressed signature against both a zero-delay and an SDF-annotated simulation, and sanity-check that fault coverage with compression matches the uncompressed ATPG run within a fraction of a percent. A larger gap signals observability loss, which you debug via the compactor's masking controls rather than by widening the MISR. For a structured walk through ATPG and compression trade-offs, see our note on ATPG fault models and coverage.
Want to go from parity trees to full on-chip compression architectures with hands-on Tessent/TestMAX labs? Explore the CourseTron DFT & Scan Compression course catalog and build real signature-analysis intuition.
Frequently asked questions
Is an XOR compactor the same as a MISR?
No. An XOR compactor is purely combinational and compacts in space — many chains to few pins, evaluated every cycle. A MISR is sequential and compacts in time — many response cycles folded into one stored signature. Production compression blocks often use both together.
Why is a 32-bit MISR considered safe?
Its aliasing probability is about 2−32, roughly one in four billion for random error patterns. That is far below the defect-escape rate from test coverage limits, so the MISR is effectively never the weak link.
Does compaction reduce fault coverage?
Ideally no. A well-designed compactor with proper X-handling preserves coverage to within a fraction of a percent of uncompressed ATPG. Measurable drops almost always trace to unmasked X-sources rather than to compaction itself.
How are unknown (X) values handled before the compactor?
Through X-masking: per-shift selectable gating logic blocks chains known to carry Xs, inserted by tools such as Tessent TestKompress or Synopsys TestMAX, so the XOR parity stays valid for the clean chains.