In short: The stuck-at fault model represents a physical defect as a single line in the circuit permanently fixed at logic 0 (SA0) or logic 1 (SA1). It is the backbone of digital manufacturing test because it is simple, technology-independent, and lets automatic test pattern generation produce a small set of vectors that catch a large fraction of real silicon defects.
A stuck at fault is an abstract model of a manufacturing defect in which a single signal line in a logic circuit behaves as if it were permanently tied to a fixed logic value, regardless of what the driving gate tries to do. The two cases are stuck-at-0 (SA0), where the line is frozen at logic 0, and stuck-at-1 (SA1), where it is frozen at logic 1. The model does not try to describe the underlying physics exactly — a short to ground, a short to power, an open gate input, or a broken metal track can all surface as the same logical symptom. Instead it reduces every such imperfection to one of two behaviours on a named net.
This deliberate simplification is what makes the model so powerful. A real chip has billions of transistors and an enormous space of possible physical failures. By mapping them onto "this line is stuck high" or "this line is stuck low", test engineers get a finite, enumerable fault list on which algorithms can reason. Each gate terminal (every input pin and every output pin) contributes two faults, SA0 and SA1, so a circuit with n fault sites has at most 2n single stuck-at faults.
Manufacturing is imperfect: dust particles, lithography variation, and metal voids mean a fraction of fabricated dies are defective. You cannot ship those, so every die is tested on an automatic test equipment (ATE) machine after fabrication. The question is which input patterns to apply. Exhaustively testing an n-input block needs 2n vectors — impossible for anything real. The stuck-at model gives a tractable target instead: generate just enough patterns to detect every modelled fault.
The industry metric for this is fault coverage — the percentage of modelled faults a test set detects. High single stuck-at coverage (typically 98–99%+) correlates strongly with low defective-parts-per-million escaping to customers, which is why the model has survived decades of process scaling even though it never literally matches a transistor-level short.
Every stuck-at test rests on two abilities, and both must succeed for the same vector:
A fault is detected only when activation and propagation hold simultaneously. Lines deep inside a design are often hard to control, hard to observe, or both — which is exactly why design-for-test techniques such as scan chains exist: they turn internal flip-flops into directly controllable and observable points, collapsing a sequential problem into a combinational one.
The classic model is the single stuck-at fault model: it assumes exactly one line is faulty at a time. This keeps the fault list linear in circuit size and is justified in practice because test sets built for single faults also catch most multiple faults as a side effect. Related and extended models include:
Many faults are logically indistinguishable, so there is no point testing each separately. Fault collapsing removes this redundancy and is a standard first step before ATPG:
Collapsing typically reduces the fault set by 50–60%, which directly cuts ATPG runtime and pattern count without lowering real coverage. The number remaining after collapsing is the collapsed fault count, the honest denominator for a coverage figure.
Some faults can never be detected by any pattern because the faulty value is masked by logic — often caused by redundant hardware. These untestable or redundant faults are excluded from the coverage denominator (reported separately as ATPG-untestable) so they do not unfairly depress the fault-coverage number. A high redundant-fault count can also hint at wasteful or unintended logic in the netlist.
Real projects and industry tool flows, with certification.
Explore CourseTron Courses →In a production DFT flow, the stuck-at model is the default fault model fed to commercial ATPG engines such as Synopsys TestMAX (formerly TetraMAX), Siemens EDA Tessent, and Cadence Modus. The typical sequence is: insert scan chains during synthesis, build the fault list and collapse it, run ATPG to generate compact patterns using D-algorithm / PODEM-style path sensitization, fault-simulate to confirm coverage, then write the patterns out in STIL or WGL format for the ATE. Engineers read the tool's summary report for test coverage (detected / detectable) and fault coverage (detected / all), and iterate — adding test points or fixing uncontrollable nets — until coverage targets are met. The same patterns are later compressed with on-chip EDT/scan-compression logic to keep tester time and data volume affordable.
Fault coverage is detected faults divided by the total fault count, including undetectable ones. Test coverage is detected faults divided by the number of detectable (testable) faults, excluding proven-untestable and redundant faults. Test coverage is the figure engineers optimise because it reflects what is physically achievable on that netlist.
Because it is finite, technology-independent, and empirically effective: test sets with high single stuck-at coverage also catch a large share of multiple, bridging, and open defects as a by-product. It is a practical proxy, deliberately simpler than the physics, that keeps ATPG tractable while still correlating with low field defect rates.
First, activation (controllability): force the faulty line to the value opposite the stuck value, so good and faulty circuits differ at that line. Second, propagation (observability): create a sensitized path that carries the difference to a primary output or scan cell, holding every side input at its non-controlling value. Both must hold in the same vector.
Fault collapsing removes logically redundant faults using equivalence and dominance relations, keeping one representative per group. It shrinks the fault list by roughly half, cutting ATPG runtime and pattern volume while leaving true coverage unchanged.
Related: boundary scan and JTAG · the VLSI Glossary · all courses.