Lockup latches in scan/clock domains

In short: A lockup latch is a level-sensitive latch inserted between two scan flops on a chain boundary so that scan-shift clock skew is absorbed by the latch's transparent window instead of racing through and corrupting the captured shift data, eliminating hold violations across skewed scan segments.

Ask any physical-design or DFT engineer what quietly breaks more scan chains than anything else, and the honest answer is clock skew during shift. Your functional timing can close beautifully at 2 GHz, your scan compression can be textbook — and then the chain fails at 10 MHz shift because one flop's scan clock arrives tens of picoseconds before the next flop's, and the shift data races forward by a bit. The lockup latch is the small, cheap, almost invisible cell that makes this problem go away. This article explains what it is, why it works, where to place it, and the traps that catch even experienced teams.

Why scan shift is a hold problem, not a setup problem

During normal (functional) operation, your static timing analysis balances setup and hold across the real clock tree, and the clock-tree synthesis engine (Synopsys ICC2, Cadence Innovus) works hard to keep skew within a tight budget — often under 50 ps at the leaf. During scan shift, however, the flops are reconfigured into one long shift register, and the launch and capture flops of adjacent bits are frequently in different clock domains, different skew groups, or even different physical regions of the die. The relationship that matters is no longer "launch clock to capture clock across one cycle" — it is simply flop A's output feeding flop B's scan input, both clocked by nominally the same shift clock.

Shift is a pure hold-dominated path. If the capture flop's clock arrives later than the launch flop's clock by more than the data-path delay plus hold requirement, the new value launched by A arrives at B before B has safely captured A's old value. One bit of the scan pattern is lost — and because every bit shifts past that boundary, the whole chain is corrupted.

You cannot "fix" this with setup margin because shift runs slowly; there is enormous setup slack. The failure is a race: positive skew on the receiving flop turns the inter-flop path into a min-delay (hold) violation. Buffer insertion helps only up to a point and is fragile across PVT corners.

What a lockup latch actually is

A lockup latch is a single level-sensitive transparent latch placed in the scan path between two flip-flops that sit across a risky clock boundary. The standard and almost universal choice is a negative-level-sensitive (active-low) latch driven by the same shift clock. It is transparent while the clock is low and holds while the clock is high.

Here is the elegant part. Both flops in a scan chain are typically positive-edge-triggered, launching on the rising edge. Insert a low-transparent latch between them and the data flow becomes two-phased:

• On the rising edge, flop A launches its new value. The lockup latch is closed (clock is high), so it holds the previous value and blocks A's new data from propagating.
• When the clock goes low, the latch becomes transparent and passes A's value through to B's scan input.
• On the next rising edge, B safely captures that value, and the latch closes again.

The latch effectively delays the data by half a clock cycle. That half-period is enormous compared to any realistic leaf-level skew (a 10 MHz shift clock has a 50 ns half period versus tens of picoseconds of skew), so even large, ugly skew between A's and B's clocks is comfortably absorbed. The hold race is gone.

Lockup latch vs. the alternatives

Rule of thumb used by most DFT flows: insert a lockup latch at every scan-chain stitch that crosses a clock domain, a voltage/skew group, a hierarchical partition boundary, or any point where the shift-clock skew can exceed the available hold margin. Tools like Synopsys DFTMAX/TestMAX and Siemens Tessent insert and verify these automatically.

Where to place them in practice

The three classic insertion points are: (1) between the last flop of one clock domain and the first flop of the next within a single chain; (2) at the boundary where a chain leaves one physical partition and enters another in a hierarchical (bottom-up) flow; and (3) immediately before the scan-out pad when the output launch sees large skew to the tester. Many teams also insert a latch at the clock-domain crossing inside on-chip compression (EDT/streaming) architectures — see our deeper treatment in scan chain architecture for how compression changes the stitching rules.

Polarity matters. If the receiving flop is positive-edge-triggered, a low-transparent (active-low) latch is correct because it delays data to the clock-low phase and presents it stably before the next rising edge. Mixing a high-transparent latch in front of a rising-edge flop reintroduces the race — a surprisingly common copy-paste bug in hand-edited stitch scripts.

How STA handles the latch

Lockup latches make shift paths safe in silicon, but they complicate static timing analysis because a latch is time-borrowing and transparent. PrimeTime and Tempus model the latch as a level-sensitive element and verify that data arrives within the transparent window and is stable before it closes. In most shift-mode analyses the margins are huge, but you must still:

• Constrain the shift clock correctly (often a slow, separate create_clock on the scan-enable mode).
• Confirm the latch library cell has valid .lib timing arcs for both the D-to-Q transparent arc and the clock-to-Q closing arc.
• Check that capture-mode (at-speed) timing is not accidentally degraded — a lockup latch sits in the scan path, so functional paths should not see it, but shared nets can create surprises.

Design teams building full custom test infrastructure — for example the services practice at Avecas VLSI design services — typically bake lockup-latch insertion rules into the DFT handoff checklist so they are never left to manual editing.

A worked number

Suppose shift runs at 20 MHz (50 ns period, 25 ns half period). Measured worst-case shift-clock skew across a domain crossing is 180 ps, inter-flop data delay is 90 ps, and the receiving flop needs 40 ps of hold. Without a latch, the effective hold requirement is 180 + 40 = 220 ps against only 90 ps of path delay — a 130 ps violation that no reasonable buffering survives at the fast corner. Insert a low lockup latch and the data is held off until the clock-low phase; the receiving flop now sees the value roughly 25 ns early relative to its capturing edge, so the 220 ps requirement is met with four orders of magnitude of margin. One 2–3 track latch turns a guaranteed chain failure into a non-issue.

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Frequently asked questions

Why use a latch instead of a flip-flop for lockup?

A transparent latch gives you the half-cycle hold-off with roughly half the area and power of a full flip-flop, and it does not add an extra clocked storage element to re-time. A negative-edge flop ("lockup flop") achieves the same half-cycle shift but is heavier; latches win on cost when you need many of them across a large design.

Do lockup latches affect functional timing?

They should not. A lockup latch sits in the scan shift path, which is active only in shift mode. Functional (mission) paths bypass it. Problems only appear if a stitch script accidentally routes functional data through the latch or shares a net, which STA in capture mode will flag.

Low-transparent or high-transparent latch?

For the usual positive-edge-triggered scan flops, use a low (active-low) transparent latch so data is handed off during the clock-low phase and is stable before the next rising edge. The polarity must match the receiving flop's edge, or the race returns.

Can I just balance the shift clock instead?

Sometimes, within a single domain. But across clock domains, voltage islands, and hierarchical partitions, perfectly balancing the shift tree is expensive or impossible, and lockup latches are the standard, robust, PVT-insensitive answer. They also guard against skew you did not anticipate.