In short: A PCB is a sandwich of copper layers (signal and plane) glued by dielectric, wrapped in solder mask, labelled with silkscreen and soldered through a paste stencil layer, and each of these appears in your CAD output as its own Gerber or ODB++ layer.
Two families of layers
When a designer says "layer", they can mean two different things. Physical layers are the real slabs inside the board: copper foil, FR-4 core, prepreg. Fabrication (documentation) layers are artwork-only: solder mask, silkscreen, paste and drill data. They carry no signal, yet a mistake in any one of them can stop a board from being built or assembled.
In Cadence Allegro, Altium Designer, Siemens Xpedition and KiCad, both families live in one stack-up manager, which is why beginners confuse them. Keep the split in mind and the rest becomes easy. If you are new to the overall flow, our PCB design flow guide shows where layer definition fits.
Signal layers: where routing happens
A signal layer is a copper layer patterned into traces, pads and small pours. Outer layers (Top and Bottom) also hold component pads, so they are crowded. Inner signal layers are quieter and are normally routed in orthogonal pairs, for example horizontal on L3 and vertical on L6, to cut crosstalk and ease escape routing.
- Microstrip: a trace on an outer layer with one reference plane below and air above. Typical 50 Ω single-ended on 0.1 mm FR-4 needs a trace near 0.18 mm wide.
- Stripline: a trace sandwiched between two planes, better shielded and slower (about 6.7 ns/m vs. 5.8 ns/m for microstrip on FR-4).
Key fact: FR-4 has a relative permittivity of roughly 4.2 to 4.5, so a 1 GHz edge sees a surprisingly short wavelength, around 14 cm in the board. That is why impedance control matters on even moderate designs.
Layers connect through vias; see via types in PCB for through, blind, buried and micro vias.
Plane layers: the return path in disguise
A plane layer is mostly solid copper dedicated to one net (GND, 3V3, 1V8). Beginners think planes exist "to carry power". They also, and more importantly, provide a continuous return path for every signal above or below them. Current follows the path of least impedance, and at high frequency that is directly beneath the trace.
Two practical consequences. First, never route a fast signal across a split in its reference plane: the return current must detour and the loop area, and therefore EMI, balloons. Second, tightly coupled power and ground planes (50 to 100 µm apart) behave as a distributed capacitor that helps decoupling above roughly 200 MHz. We go deeper in signal integrity in PCB.
Solder mask: the green coat that is really a stencil
Solder mask (also "solder resist") is a photo-imageable polymer, about 20 to 25 µm thick, that covers copper everywhere except where you want to solder. It stops solder bridging between fine-pitch pads and protects copper from oxidation. Green dominates because of supplier inertia and inspection contrast; black and white look nicer but make AOI harder.
The key concept: the mask layer in your CAD file is a negative. You draw openings, not coverage. In most tools every SMD and through-hole pad automatically gets a mask opening about 50 to 75 µm larger per side than the pad (the "mask expansion"). If the web between two openings is thinner than roughly 100 µm, the fabricator may remove it and create a solder bridge risk, which is a classic problem on 0.4 mm pitch BGAs and QFNs.
Paste layer: the assembly stencil
The paste layer (Paste Top / Paste Bottom) is never etched into the board. It is the artwork used to cut a thin stainless-steel stencil (typically 100 to 130 µm thick) through which solder paste is printed before reflow. Apertures normally match pads 1:1 but are often shrunk 10 to 20 percent, or split into windowpane patterns on large thermal pads so the part does not float.
Key fact: the area ratio (aperture area divided by aperture wall area) should be above about 0.66 for clean paste release. Fail this and tiny pads print starved.
Silkscreen: legend, not decoration
Silkscreen (legend) is epoxy ink printed on the mask. It carries reference designators, pin-1 marks, polarity and logos. Rules that bite: keep ink off exposed pads (the fabricator clips it anyway), use a minimum line of about 0.15 mm and text height of at least 0.8 mm, and never put it where it hides a via test point. These checks belong in your PCB design rules set, and fabrication limits are covered in PCB design for manufacturing.
Copper foil weights and how it all appears in the file
Copper foil is specified by weight per square foot. Weight sets thickness and, with it, current capacity and etching limits.
| Foil weight | Thickness | Typical use |
|---|---|---|
| 0.5 oz | about 17 µm | Fine-pitch inner signal layers |
| 1 oz | about 35 µm | Standard outer and inner layers |
| 2 oz | about 70 µm | Power boards, high-current traces |
A 1 oz outer layer ends up a little thicker after plating, which is why outer layers need wider minimum trace and space than 0.5 oz inner layers. Stack-up decisions, including dielectric height for controlled impedance, are covered in PCB stackup design and multilayer PCB design.
When you click "generate outputs", every layer becomes a separate file. Gerber RS-274X (or the richer ODB++ / IPC-2581 single-package formats) is what the fabricator reads. A typical KiCad-style set looks like the figure below.
Watch the polarity trap: positive layers draw copper where there is artwork, whereas mask and some legacy plane layers are negative. Always load the Gerbers into a viewer (KiCad GerbView, CAM350, or the fabricator's online checker) before releasing. Our practical PCB design standards article covers IPC rules that govern these checks.
If you want hands-on practice with these exports in a mentored setting, Avecas design services run real board projects, and our CourseTron courses teach the full flow.
Frequently asked questions
Is the paste layer printed on the PCB?
No. Paste is used only to make the assembly stencil. The bare board never carries it.
Why are plane layers sometimes shown inverted?
Older tools drew planes as negatives: artwork shows where copper is removed (clearances and thermals). Modern tools let you choose, but you must know which convention your fabricator expects.
Does solder mask thickness affect impedance?
Slightly. Mask over a microstrip lowers its impedance by a couple of ohms, so good field solvers include it in the model.
How many layers do I need?
Count signals that need controlled impedance and reference planes, then add power. Simple boards use two, while most processor boards use four to eight.
References & Further Reading
Ready to design real boards? Explore our PCB design track in the CourseTron courses, or see ChipXpert for instructor-led training.