PCB stackup design

Key fact: For a 50 Ω single-ended microstrip on standard FR-4 (Dk ≈ 4.3), a 0.2 mm wide trace typically needs about 0.1 mm of dielectric to its reference plane. Change that spacing and the impedance changes with it — which is why the stackup must be fixed before you route.

Layer count: how many copper layers do you need?

Layer count is driven by routing density, the number of power rails, and your signal-integrity requirements — not by the board outline alone. A rough progression:

• 2 layers — low-cost, low-speed designs. There is no dedicated plane, so return paths are poor and this is unsuitable for fast edges.
• 4 layers — the workhorse. A common order is Signal / Ground / Power / Signal, giving each outer signal layer an adjacent plane.
• 6 to 8 layers — needed for dense BGAs, multiple supplies, and high-speed buses such as DDR or PCIe, where you want signals sandwiched between planes.
• 10+ layers — complex SoC boards, high pin-count fan-out, and strict EMI budgets.

The governing rule is simple: every signal layer should be adjacent to a reference plane. If you cannot satisfy that, add layers.

Signal and plane ordering — the return path

High-speed current does not flow only in the trace; an equal and opposite return current flows in the nearest plane, directly beneath the signal. When a plane sits next to every signal, the return path is tight, the loop area is small, and radiated emissions and crosstalk drop sharply.

This is why the ordering matters as much as the count. Placing two signal layers back-to-back with no plane between them, or forcing a signal to reference a plane two layers away, forces the return current to detour — enlarging the loop and injecting noise.

Watch the signal referencing its plane

The animation below shows a switching edge travelling along a trace while its return current mirrors it in the plane underneath — the pair stays tightly coupled only because a plane sits directly below the signal layer.

Dielectric material and thickness

The insulating layers between copper are built from cores (cured laminate with copper on both faces) and prepreg (uncured glass-epoxy that bonds the stack during lamination). Two material properties dominate:

• Dielectric constant (Dk / εr) — sets propagation speed and impedance. Standard FR-4 sits near 4.2–4.5; low-loss materials like Rogers run 3.0–3.5.
• Loss tangent (Df) — how much energy the dielectric absorbs. At multi-gigahertz speeds, high Df causes severe attenuation, so RF and >10 Gbps designs move to low-Df laminates.

Thickness matters just as much: the distance from a trace to its reference plane directly sets impedance. Thinner dielectric lowers impedance for a given trace width and tightens coupling. Always use your fabricator's published stackup (their real Dk and thickness) rather than generic assumptions.

Impedance control

Controlled impedance means the trace geometry and dielectric are chosen so a line presents a target impedance — typically 50 Ω single-ended, or 90/100 Ω differential for USB, Ethernet, and similar buses. The main levers are:

• Trace width — wider traces lower impedance.
• Dielectric height to the reference plane — thinner lowers impedance.
• Dielectric constant of the material.
• Copper thickness and whether the trace is a surface microstrip or a buried stripline.

You compute these with a 2D field solver or the fabricator's impedance calculator, then call out the controlled-impedance lines on a fab drawing so the board house can adjust geometry to hit the spec during manufacturing.

Cost drivers

Stackup choices move the price of a board more than almost any other decision:

• Layer count — each added pair of layers increases material, lamination, and drilling cost.
• Material — low-loss laminates can cost several times more than FR-4.
• Via technology — blind, buried, and microvias (common in HDI boards) add sequential lamination steps and raise cost steeply.
• Controlled impedance — impedance testing and tighter tolerances add a modest premium.
• Finished thickness and copper weight — heavier copper for power boards changes etching and spacing.

The engineering goal is the lowest layer count and simplest via structure that still satisfies routing density and signal integrity — over-building wastes money, under-building causes respins.

pcb stackup design — FAQ

Why does every signal layer need an adjacent reference plane?

Because high-speed return current flows in the nearest plane directly under the trace. An adjacent plane keeps that return loop small, which minimizes radiated emissions, crosstalk, and ground bounce. Signals without a nearby plane create large loops that act as antennas.

What is the difference between core and prepreg?

A core is fully cured laminate with copper already bonded to both sides, giving a stable, predictable thickness. Prepreg is uncured glass-epoxy that melts and bonds the layers together during lamination. A stackup alternates cores and prepreg to reach the target layer count and finished thickness.

Is 4 layers always enough?

For many designs with one or two supplies and moderate speeds, yes — a Signal/GND/PWR/Signal stack works well. But dense BGAs, multiple power rails, or high-speed buses like DDR usually need 6 or more layers so signals can be sandwiched between planes and routed without compromising return paths.

How is controlled impedance actually achieved?

You fix the stackup (dielectric height and material), then size trace widths with a field solver to hit the target impedance, and finally mark those nets as controlled-impedance on the fab drawing. The board house fine-tunes geometry and verifies the result with impedance test coupons.

Related: PCB design flow · Glossary · all courses.