In short: A PCB design-rule check (DRC) is the automated gatekeeper that compares your layout against the fabricator's physical limits — minimum copper-to-copper clearance, trace width, drilled-hole size, and the annular ring left around each via — so that what you tape out can actually be etched, drilled, and plated without shorts or opens.
Every board house publishes a "capability" table, and your EDA tool turns that table into a machine-checkable rule set. Run the DRC before you release Gerbers and you catch the acid trap, the sliver, and the tangent via that would otherwise surface as a scrapped panel weeks later. This article walks through the four constraint families a DRC enforces, with the numbers that matter for a typical 2-layer, 1 oz-copper, 6/6 mil process.
Why the DRC exists: physics, not pedantry
A fabricator does not draw your copper — it removes everything you did not draw, using photoresist and an etchant, then drills and electroplates the holes. Each of those steps has tolerance. Etchant undercuts copper sidewalls; drills wander; registration between layers drifts by a few mils. The DRC encodes the margins that keep those tolerances from turning adjacent features into one feature (a short) or eroding a thin feature into nothing (an open). It is the same discipline a chip's foundry DRC enforces in Cadence Pegasus or Siemens Calibre — just at millimetre scale instead of nanometre.
⚙️ A "mil" in PCB work is one-thousandth of an inch (0.0254 mm), not a millimetre. A 6 mil trace is 0.152 mm wide. Mixing the two units is the single most common DRC-setup error for newcomers.
Clearance: keeping copper apart
Clearance is the minimum edge-to-edge gap between any two independent copper features — trace to trace, trace to pad, pad to pad, copper pour to track. On a standard process this is typically 6 mil (0.15 mm), dropping to 4 or even 3.5 mil on an advanced/HDI line at a cost premium. The limit comes from etch resolution: if two copper edges sit closer than the process can reliably clear, the etchant leaves a bridge of copper between them — a short that no amount of rework fixes.
Clearance also has an electrical dimension the geometric rule must respect. For creepage and air-gap on mains-voltage nets, IPC-2221 pushes spacing far beyond the fab minimum — roughly 0.1 mm per volt for internal layers at low altitude, so a 230 V AC net wants millimetres, not mils. A good rule set uses net-class-aware clearances: a HIGH_VOLTAGE class with a 2.5 mm rule overrides the default 6 mil everywhere those nets go.
Trace width: carrying current without cooking
Minimum trace width is set by two independent limits, and the DRC enforces both. First, the manufacturing floor — the thinnest line the process can etch repeatably (6 mil standard, 3 mil on fine-line). Second, the current-carrying requirement, derived from IPC-2152. A 1 oz (35 µm) external trace carrying 2 A with a 10 °C rise needs roughly 20 mil of width; push to 5 A and you need about 90 mil or a copper pour. The DRC catches the first; a width-calculator or a width-by-net-class rule enforces the second.
| Net class | Width (1 oz, ext.) | Approx. current (10 °C rise) |
|---|---|---|
| Signal | 6 mil | ~0.5 A |
| Power (3.3 V) | 20 mil | ~2 A |
| Power (battery/main) | 50 mil | ~3.5 A |
| High current | pour / 90 mil | ~5 A |
Width rules also underpin controlled impedance. A 50 Ω single-ended microstrip on a given dielectric demands a specific width; your DRC/length-tuning setup treats that width as a hard constraint, not a suggestion, so autoroute and manual edits cannot narrow it.
Vias and annular ring: surviving the drill
A via is a plated hole joining layers. It has three governed dimensions: the finished hole size (what the drill plus plating leaves, e.g. 0.3 mm), the pad diameter, and the difference between them split as a ring — the annular ring. IPC-6012 Class 2 asks for a minimum 2 mil (0.05 mm) ring after the drill is allowed to wander within its registration tolerance; Class 3 is stricter and forbids any breakout at all.
? Annular ring math: ring = (pad_dia − hole_dia) / 2 − registration_tol. With a 0.6 mm pad, 0.3 mm hole, and ±0.075 mm registration, you keep (0.6−0.3)/2 − 0.075 = 0.075 mm of ring — comfortably above the 0.05 mm Class 2 floor.
The failure mode the DRC guards against is breakout: the drill drifts enough that the hole breaks the edge of the pad, exposing bare laminate and weakening the plated barrel. The related tangency and acid-trap checks catch two more drill hazards — a via placed so a track meets a pad at an acute angle (where etchant pools) and a via pad that overhangs the board edge.
How the checks run in a real flow
In KiCad, Altium Designer, or Cadence Allegro, rules live in a constraint manager keyed to net classes and board regions. You set the base process (say the JLCPCB or your house 6/6 capability), add overrides for power and high-voltage classes, then run an online DRC that flags violations live as you route plus a batch DRC before output. The batch pass produces a violation list — "clearance 5.4 mil < 6 mil", "annular ring 0.03 mm < 0.05 mm" — each hyperlinked to the offending geometry.
Fab houses run their own incoming DRC on your Gerbers and will either email an engineering query or, worse, silently "fix" a marginal feature. Owning the rule set yourself — and keeping it in sync with the chosen process, as covered in our design-for-manufacturing guide — is how you stay in control of the result. For teams moving from hobby boards to production, our companion on stackup and controlled impedance explains how width and clearance rules change the moment layer count and dielectric enter the picture. If you need a board designed and signed off for you rather than learned from scratch, Avecas offers hardware design services that ship DRC-clean Gerbers.
Want to run a full DRC on a real board and read the violation report like an engineer? The CourseTron PCB Design track takes you from schematic to fab-ready Gerbers with hands-on constraint-manager labs.
Frequently asked questions
What is the difference between clearance and creepage?
Clearance in a DRC is the drawn copper-to-copper gap set by etch resolution. Creepage is the shortest path along the surface of the laminate between two conductors, and for safety-critical mains nets it must be larger than the bare etch minimum — governed by IPC-2221 and the relevant safety standard, not the fab's capability sheet.
Why does my DRC pass but the board house still raises a query?
Your rule set probably used the fab's absolute minimums, which leave no margin for yield. Fab houses prefer features above their floor. Set your DRC a notch tighter than the datasheet (e.g. route at 8 mil when the process allows 6) so your "pass" has headroom.
How small can the annular ring be?
IPC-6012 Class 2 allows a 0.05 mm (2 mil) minimum ring after drill registration; Class 3 forbids any breakout, effectively demanding more pad-to-hole margin. Always design to the class your application requires, not the smallest number the fab quotes.
Does a DRC check signal integrity?
A geometric DRC checks physical manufacturability. Impedance, length matching, and crosstalk are handled by separate constraint-driven rules in tools like Cadence Allegro or Siemens Xpedition — related, but a distinct rule domain from the clearance/width/via set.