In short: OrCAD Capture holds the logical design, a netlist (pstxnet.dat, pstxprt.dat, pstchip.dat) carries it into Allegro PCB Editor, and Constraint Manager keeps electrical and physical rules attached to nets so placement and routing are checked live against them.
Why the Capture-to-Allegro handoff matters
A schematic is a statement of connectivity and intent. A board is a statement of geometry. Most late-stage respins on complex boards (DDR4 memory, PCIe Gen4, 48-volt power stages) trace back to intent that was lost between those two statements: a length-match requirement lived in someone's notebook, a differential pair was never declared, or a footprint pin map disagreed with the symbol. The OrCAD Capture to Allegro PCB Editor flow exists to carry intent, not only connections, across that boundary.
If you are new to the overall sequence, read our PCB design flow overview first. This article zooms into one vendor flow and explains each stage the way an interviewer would probe it.
Stage 1: Capture design hygiene before any netlist
Netlisting only reports what Capture knows. Three habits prevent most trouble:
- Footprint property on every part. The PCB Footprint property must name a real Allegro .psm footprint. A missing or misspelled value produces a netlist-time error and, worse, sometimes a wrong-but-valid footprint.
- Design rule check in Capture. Run DRC for unconnected pins, duplicate references and power pins with no net. A floating VDD pin on a 0.5 mm BGA is much cheaper to find here.
- Net naming discipline. Names such as DDR_DQ0 or PCIE_TX0_P are what constraint templates and bus-aware tools will later match. Name once, name consistently.
Key fact: Capture CIS adds a component database (Part Manager / DBC), so the footprint, manufacturer part number and tolerance travel with the symbol and are not retyped by hand.
Stage 2: The netlist, what it actually contains
Capture's Allegro netlister writes a set of text files, typically in an allegro folder: pstxnet.dat (nets and the pins on them), pstxprt.dat (each reference designator mapped to its device and footprint) and pstchip.dat (device definitions with pin-number to pin-name mapping). Allegro PCB Editor reads them through File > Import > Logic.
PCB Editor: File > Import > Logic
Import logic type : Design entry CIS (Capture)
Place changed component : Always
Allow etch removal during ECO : unchecked (safer first time)The import compares the new netlist to the existing board and applies only the delta. That is why re-importing is routine: swap a resistor value or change a net name and only that object moves. Import also checks that every footprint exists in the PSMPATH and PADPATH search paths. Nearly every first-import failure on a new project is a library path issue, not a design issue.
Stage 3: Constraint Manager as the single source of rules
Constraint Manager (CM) is where intent becomes enforceable. It uses a spreadsheet-like view organised in worksheets: Electrical, Physical, Spacing, Same Net Spacing, and Manufacturing. Constraints attach to objects: nets, net classes, buses, differential pairs and match groups.
- Physical rules: line width, via type, neck width. A 50 ohm single-ended net on a 4 mil dielectric might be 5.5 mil wide; the same net may neck to 4 mil under a BGA.
- Spacing rules: clearance by class pair. For example 4 mil default, 12 mil between clock nets and everything else to limit crosstalk.
- Electrical rules: maximum length, relative propagation delay, differential-pair phase tolerance, and topology (fly-by for DDR address/command).
The widely used trick is net classes plus constraint inheritance: define a DDR_DATA class once and every member inherits width, spacing and length rules. Pair this with a stackup that matches your impedance targets (see PCB stackup design), because a width rule is only as good as the dielectric behind it. General rule definitions are discussed in PCB design rules.
| Constraint type | Example value | Why it exists |
|---|---|---|
| Differential impedance | 90 ohm USB / 100 ohm PCIe | Limits reflections on the link |
| Byte-lane match | DQ within 25 mil of DQS | Preserves setup/hold at the receiver |
| Pair phase tolerance | 2 mil within a pair | Keeps P and N edges aligned, limits mode conversion |
| Max stub length | 100 mil on a clock | Avoids reflections from stubs |
Key fact: Rules in Constraint Manager are live. Allegro displays DRC markers (and, for timing rules, a negative or positive margin) while you route, so you correct a violation as it happens, not at the end.
Stage 4: Placement driven by connectivity and constraints
Placement on a complex board is a sequence, not a scatter. A common order: fixed mechanical items (connectors, mounting holes, keep-outs) first, then the large BGA or SoC, then memory with decoupling, then power stages, then everything else.
- Room and Quickplace. Assign components to rooms so a functional block stays together; Quickplace can auto-seed a first pass by net connectivity.
- Cross-probing. Select a part in Allegro and it highlights in Capture. This is how a layout engineer questions a schematic decision without email.
- Decoupling geometry. Put the smallest capacitor (for instance 100 nF in 0402) closest to the power ball and keep the via-to-pad loop short; loop inductance, not capacitance value, dominates above ~100 MHz.
- Swap functions. Pin swap and gate swap can untangle a congested FPGA fan-out, but swaps must be back-annotated to Capture or the schematic lies.
Dense parts push you toward finer vias and microvias. When a 0.5 mm pitch BGA cannot be escaped with through vias, review HDI PCB design and the layer strategy in multilayer PCB design before committing to a stackup.
Stage 5: Routing, tuning and verification
Interactive routing in Allegro honours constraints continuously. You push-and-shove, route pairs together, and use the Delay Tune or Accordion tools to hit length targets. Autorouting (the Allegro PCB Router) is used sparingly, mainly on low-speed bulk nets after critical nets are locked.
A DDR byte lane shows the logic. Suppose DQS is 1,820 mil and the constraint is DQ within 25 mil of DQS. A DQ at 1,780 mil is 40 mil short and flagged. Tuning adds roughly 40 mil of serpentine, using gaps of at least three times the trace width so the meanders do not couple to themselves.
Before release, run the checks in sequence: DRC (Tools > Update DRC), a constraint report from CM, antenna and dangling-line checks, and a manufacturing review against PCB design for manufacturing. Signal-integrity pre-route and post-route simulation, for instance with Sigrity, closes the loop where raw length rules are not enough.
Key fact: Length matching is a proxy. Real timing depends on propagation delay, which differs between outer (microstrip) and inner (stripline) layers; Allegro can constrain delay in picoseconds instead of mils to account for this.
Common mistakes interviewers ask about
- Importing a netlist with the wrong PSMPATH so footprints silently resolve to stale copies.
- Defining constraints per net instead of per class, creating hundreds of unmaintainable overrides.
- Pin or gate swaps in layout that never reach Capture, so the schematic and the board diverge.
- Ignoring return paths: a perfectly length-matched pair that crosses a plane split still radiates. See PCB EMI/EMC design.
Teams that need hands-on help on production boards often bring in outside layout capacity; Avecas design services is one such option for engineering support.
Want guided labs on schematic capture, constraints and routing? Explore the PCB tracks in our CourseTron courses and build a board end to end.
FAQ
What files does the OrCAD netlist produce for Allegro?
The Allegro netlister writes pstxnet.dat, pstxprt.dat and pstchip.dat. Together they describe nets, component-to-footprint mapping and device pin definitions, and Allegro imports them via File > Import > Logic.
Where should length and impedance rules be defined?
In Allegro Constraint Manager, attached to net classes, buses and differential pairs. Net classes keep the rules maintainable and let new nets inherit them automatically.
How do layout changes get back into the schematic?
Through back-annotation: Allegro exports pin swaps, gate swaps and reference designator changes, and Capture applies them so both databases stay consistent.
Is autorouting used for complex boards?
Mostly for non-critical, low-speed nets. High-speed interfaces are routed interactively with constraints, then tuned and verified.
References & Further Reading
More electronics training is available from our sister brand ChipXpert.