In short: A KiCad project moves through six gates (schematic and ERC, footprint assignment, layout, DRC, plotting, and a fab-side check), and interviewers want to hear what each gate catches that the previous one cannot.
The six gates of a KiCad project
KiCad is the open-source suite many hardware startups, universities and consultancies now use, so questions about it show up in PCB interviews even at companies that run Altium or Cadence Allegro in production. The tool matters less than the flow. Every board, whatever the CAD package, goes through the same logic: capture intent, bind it to physical parts, place and route, prove it obeys rules, and hand a manufacturer an unambiguous data package. If you need a refresher on what the finished product is, start with what a PCB actually is.
Schematic capture and ERC
In the schematic editor you place symbols, wire nets and add power flags. The Electrical Rules Check (ERC) reads pin types, so an output tied to another output, an input left floating, or a power input with no driving power output gets flagged. The classic beginner trap is the "power input pin not driven" error on a regulator's output rail: the fix is a PWR_FLAG on the net, which tells the checker that something real supplies it.
Key fact: ERC proves the netlist is self-consistent, not that the circuit works. A 3.3 V sensor wired to a 5 V rail passes ERC perfectly.
Interviewers often ask what you do beyond ERC. Good answers: review each datasheet's absolute maximum ratings against your rail, check pull-ups on I2C (typically 2.2 kΩ to 4.7 kΩ at 400 kHz), confirm strap pins on microcontrollers, and add decoupling per power pin (usually 100 nF close to the pin plus a bulk capacitor per rail). Fill in Value, Manufacturer and MPN fields now, because the bill of materials is generated from them later.
Footprint assignment: where most respins start
A symbol is abstract; a footprint is physical copper. Assigning the wrong one is the most common cause of a board that cannot be assembled. A 0603 resistor symbol is the same as a 0805 one, but the pads differ by about 0.4 mm. Names follow IPC-7351-style conventions, for example R_0603_1608Metric, where 1608 means 1.6 mm by 0.8 mm.
- Verify every non-passive footprint against the manufacturer's recommended land pattern, not just the package name. Two QFN-32 parts can have different thermal pad sizes.
- Check pin 1 marking and courtyard. KiCad's courtyard layer (F.CrtYd) is what prevents parts from overlapping during DRC.
- Run the symbol-to-footprint pin-count check before updating the PCB from the schematic.
When you push the netlist to the layout editor, KiCad draws ratsnest lines: thin straight connections showing which pads must be joined. These are the to-do list for routing.
Layout: stackup, placement and routing
Layout begins with board setup rather than routing. Set the stackup (for a typical 4-layer board: signal, ground, power, signal, around 1.6 mm total), minimum track width, clearance, via size and drill, and define net classes. A sensible low-cost fab rule is 0.15 mm trace and space with a 0.3 mm drill, but check the vendor's capability table first, because tighter values cost more.
Placement decides the quality of the result. Put connectors on the edge, decoupling capacitors within 2 to 3 mm of their pins, and the crystal right beside the oscillator pins. Then route critical nets first: clocks, differential pairs, and power. Width for power nets follows from current and allowable temperature rise, which our guide on trace width and current capacity works through; a 1 A net on 1 oz outer copper with a 10 °C rise needs roughly 0.3 mm. Choose your vias deliberately too, since through, blind and buried options change both cost and routability, as explained in via types in PCB.
Finally pour ground zones. Pads connected to a plane through a solid connection are hard to solder, so KiCad uses thermal spokes; see thermal reliefs and teardrops for the trade-offs.
Key fact: Zones are not filled live. Always press B (refill all zones) before running DRC, or the checker works on stale copper.
DRC: what it catches and what it cannot
The Design Rules Check measures geometry: copper-to-copper clearance, minimum track width, annular ring (the copper left around a drilled hole, commonly 0.13 mm minimum), drill-to-drill spacing, silkscreen over pads, and unconnected items. It also compares the board against the schematic, so a missing net is reported.
What DRC cannot do is judge electrical performance. It will not warn that a high-speed trace crosses a plane split, that a return path is broken, or that a differential pair is skewed by 20 mm. For RF boards those rules live in your head and in layout practice, such as the ones in RF PCB layout guidelines. Note that every DRC exclusion needs a written justification; reviewers distrust boards with silently waived errors.
Gerber and drill export
Plotting converts each layer into an RS-274X Gerber file, a vector description of apertures and strokes. Typical output for a 4-layer board is eleven or so files: four copper layers (.gtl, .g2, .g3, .gbl), two solder masks, two silkscreens, two paste layers (if stenciled) and the Edge.Cuts outline. Drill data goes into Excellon files, with plated and non-plated holes separated. The details of each file type are in Gerber files explained.
Two habits separate experienced engineers. First, use the same drill origin for Gerbers and drill files (the auxiliary axis origin), or holes land offset from pads. Second, always open the zip in an independent viewer such as KiCad's Gerber viewer or the fabricator's online preview. Many vendors expect the Gerber X2 attributes that tell their CAM software which file is which layer.
What interviewers actually ask
| Question | Strong answer includes |
|---|---|
| What does ERC miss? | Voltage compatibility, wrong values, missing decoupling |
| A board came back with the connector mirrored. Why? | Footprint pin order not checked against the datasheet, viewed from the wrong side |
| DRC is clean but the board fails. Why? | Signal integrity, return paths and thermal issues are outside DRC |
| Why do holes sit off-center? | Mismatched origin between Gerber and drill files |
Expect scenario questions rather than menu trivia. Narrate your process: what you checked, what could still be wrong, and how you would find out. The fastest way to build that habit is guided practice; our PCB design courses take you through full projects, and the hands-on training team at ChipXpert runs placement-oriented batches if you want mentoring on top.
Ready to build real boards? Join a CourseTron PCB course and take a project from schematic to fabricated Gerbers, with reviews at every gate. Browse all courses.
Frequently asked questions
Does a clean ERC mean my schematic is correct?
No. ERC checks connectivity rules against pin types. It cannot know that a part is powered from the wrong voltage or that a resistor value is wrong.
Why must I refill zones before DRC?
Copper pours are computed on demand. If you have moved a track since the last fill, the stored copper is out of date and DRC may miss a clearance violation.
Which files do I send to the fabricator?
The Gerber layers for copper, mask, silkscreen and outline, plus Excellon drill files, usually zipped. Add a pick-and-place file and BOM only if you order assembly.
Is KiCad accepted in industry?
Yes for many small and mid-size teams. The concepts transfer directly to Altium, OrCAD and Allegro, which is why interviewers focus on the workflow.