In short: PCB trace width is sized from the current it carries and the allowable temperature rise using the IPC-2221 charge-and-cross-section relationship, where copper weight sets thickness and width sets the rest of the cross-sectional area that keeps the conductor cool.
Every net on a board that moves real current, power rails, motor drives, LED strings, battery feeds, has to be wide enough that its own resistive heating does not cook the copper or the laminate around it. Get it wrong and you get a trace that runs 40 °C hot, delaminates the FR-4, or in the worst case fuses open like a slow blow element. This is one of the most common board-level interview questions precisely because it ties together Ohm's law, thermodynamics, and manufacturing reality in one small decision.
Why a trace heats up at all
A copper trace is just a resistor. Its DC resistance is R = ρ·L / A, where ρ is copper's resistivity (about 1.72 × 10⁻⁸ Ω·m at 20 °C), L is length, and A is the cross-sectional area. Push current I through it and it dissipates P = I²R watts as heat. That heat has to escape, mostly by conduction into the board and convection off the surface. The trace stabilizes at whatever temperature makes heat-out equal heat-in. The design goal is to keep that equilibrium temperature rise, ΔT above ambient, inside a budget you choose: typically 10 °C for conservative consumer work, 20 °C or 30 °C where you can tolerate warmer copper.
Copper also has a positive temperature coefficient of about 0.39%/°C, so a hot trace is a more resistive trace, which dissipates even more, a mild runaway that the thermal model has to account for.
Copper weight sets the thickness
You do not choose trace thickness directly; you choose a copper weight and the fab applies it to the whole layer. Copper weight is quoted in ounces per square foot. The workhorse numbers:
- 0.5 oz ≈ 17.5 µm thick
- 1 oz ≈ 35 µm, the default for most outer layers
- 2 oz ≈ 70 µm, common for power boards
- 3 oz ≈ 105 µm and heavy-copper processes go well beyond
Double the copper weight and you double the cross-section for the same width, which roughly doubles current capacity for a given ΔT. That is why 2 oz copper is the cheapest lever for a tight power layout before you start widening traces or pouring copper planes.
Internal (buried) layers carry roughly half the current of an external layer at the same width and ΔT, because they are sandwiched in laminate with far worse convective cooling. IPC-2221 bakes this directly into separate constants for internal vs. external conductors.
The IPC-2221 formula
The industry reference is IPC-2221 (the successor to the old IPC-D-275 charts). It gives current as a function of allowable temperature rise and cross-sectional area:
I = k · ΔT0.44 · A0.725
Here I is in amps, ΔT is the temperature rise in °C, A is the cross-section in square mils, and k is an empirical constant: 0.048 for external layers and 0.024 for internal layers. Rearranged for area: A = (I / (k·ΔT0.44))1/0.725. Divide A by the copper thickness (in mils) to get the required width.
Worked example: a 3 A rail on an external 1 oz layer with a 10 °C rise budget. 1 oz ≈ 1.37 mils thick. Solving, A ≈ (3 / (0.048 · 100.44))1.379 ≈ 54 square mils, so width ≈ 54 / 1.37 ≈ 39 mils (about 1.0 mm). Relax the budget to 20 °C and the required width drops to roughly 24 mils, because the ΔT0.44 term lets you trade temperature headroom for copper.
| Current | Width (mils) | Width (mm) |
|---|---|---|
| 0.5 A | ~5 | 0.13 |
| 1 A | ~12 | 0.30 |
| 3 A | ~39 | 1.00 |
| 5 A | ~75 | 1.90 |
| 10 A | ~200 | 5.10 |
Where the simple formula stops being enough
IPC-2221 assumes a lone trace in still air. Real boards violate that constantly, and this is exactly the nuance interviewers probe for:
- Adjacent traces and parallel power raise local ambient temperature, so neighbouring hot traces must be de-rated.
- Vias are the usual bottleneck. A single 0.3 mm plated via carries far less than the trace feeding it; power nets need vias in parallel or large thermal stitching.
- Connectors and pads often limit the whole net before the trace does.
- Pulsed vs. continuous current: a trace that would fuse at 10 A DC can pass short pulses far above that, because the thermal mass has not had time to heat.
IPC-2152 (2009) is the modern, more accurate standard, built from thermal measurements that account for board thickness, plane proximity, and dielectric conductivity. Serious power work uses IPC-2152 charts or a thermal solver. Tools such as Siemens HyperLynx, Cadence Allegro's electrical/thermal checks, and Ansys-class field solvers let you simulate copper temperature instead of trusting a 1998 curve fit; Synopsys and Cadence signoff flows apply current-density (electromigration/IR-drop) rules to confirm no net is undersized before fab.
Rule of thumb for a quick sanity check on external 1 oz copper at ~10 °C rise: about 1 A per 12 mils (0.3 mm) of width up to a few amps. Above ~5 A, switch to 2 oz copper or a copper pour rather than an impractically wide trace.
Current capacity is only half of signal integrity, though. On high-speed nets the controlled dimension is not current but characteristic impedance, which depends on width, dielectric height and stack-up; see our companion piece on impedance matching in PCB design. For how return current and plane cutouts interact with wide power traces, see ground plane and return-path design. If you want a hands-on board brought to manufacture, the team at Avecas PCB and hardware design services runs power-integrity and thermal signoff as part of layout.
Want to go from "wide enough, I think" to a board you can defend in a design review? CourseTron's PCB design track walks through IPC-2221, IPC-2152 and real thermal simulation on live boards. Explore the CourseTron PCB courses →
Frequently asked questions
Is width or copper weight the better way to add current capacity?
Copper weight is usually cheaper and more area-efficient: moving from 1 oz to 2 oz roughly doubles capacity without widening any trace or disturbing routing. Widening traces costs board real estate. Many power designs combine both, plus copper pours for the heaviest rails.
What temperature rise should I design for?
10 °C is a safe, conservative default for consumer electronics. 20–30 °C is acceptable where the board already runs warm or space is tight, provided the laminate's Tg (glass-transition temperature) and nearby components tolerate it. The rise is above local ambient, not room temperature, so account for enclosure heating.
Why do internal traces need to be wider than external ones?
Buried layers cannot shed heat by convection; they rely on conduction through laminate, which is a poor thermal path. IPC-2221 captures this by halving the k constant (0.024 vs. 0.048), so an internal trace needs noticeably more cross-section for the same current and ΔT.
Does IPC-2221 account for vias and connectors?
No. It models a straight, uniform trace only. Vias, pads, and connectors are separate thermal and current-density limits that you must check independently, and they are frequently the real bottleneck on a power net.