PCB

Rf PCB Layout Guidelines

By CourseTron Team ·  7 min read ·  Updated Oct 2026 💬 𝕏 in f
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    In short: RF and microwave PCB layout is dominated by controlled-impedance transmission lines, continuous low-inductance ground, and component placement that keeps current loops tiny — because at GHz frequencies every trace, via, and gap is a circuit element, not just a wire.

    Below roughly 50 MHz a trace is just a connection. Above a few hundred MHz, the same trace becomes a transmission line, a radiator, and a resonator all at once. RF and microwave layout therefore trades schematic-level thinking for field-level thinking: you lay out the return path and the dielectric as carefully as the signal itself. This guide walks through the three rules that separate a working 2.4 GHz board from a mysteriously lossy one — grounding, transmission lines, and placement — with concrete numbers you would be expected to defend in an interview.

    Why "high frequency" changes everything

    A signal travels in a PCB dielectric at roughly c/√εr. On FR-4 (εr ≈ 4.3) that is about 1.4×10⁸ m/s, giving a wavelength of ~61 mm at 2.4 GHz and ~12 mm at 12 GHz. The practical rule: once a trace length exceeds about λ/10 you must treat it as a transmission line. At 2.4 GHz that threshold is ~6 mm — shorter than many component-to-component runs. Ignore it and you get reflections, standing waves, and insertion loss that no amount of firmware will fix.

    Key fact: FR-4 loss tangent (tanδ ≈ 0.02) makes it marginal above ~6 GHz. Serious microwave boards move to Rogers RO4350B (εr 3.48, tanδ 0.0037) or PTFE laminates precisely because dielectric loss scales with frequency × tanδ.

    Grounding: the return current is the real signal

    At RF, return current does not spread across the whole ground plane — it hugs the region directly under the trace, because that path has the lowest loop inductance. This single fact drives every grounding rule:

    • Keep the reference plane continuous. A slot or split under a microstrip forces the return current to detour around it, enlarging the loop, adding inductance, and creating a slot antenna. Never route a split-plane gap beneath an RF trace.
    • Stitch grounds with vias, generously. A via is ~0.5–1 nH; at 2.4 GHz that is ~15 Ω of reactance. Place ground vias every λ/20 (≈3 mm at 2.4 GHz) along coplanar structures and around shield walls so the plane behaves as one node.
    • Use a via fence around sensitive lines. Two rows of stitching vias on either side of a coplanar waveguide form a quasi-coax that suppresses surface-wave coupling between a PA output and an LNA input.
    Return current under a microstrip Signal trace (microstrip) Return current concentrates under the trace Continuous ground plane (return path) A slot here detours the return: more loop inductance and radiation CourseTron · coursetron.com
    Return current follows the path of least loop inductance — directly beneath the trace. Any gap in that plane is a defect.

    Transmission lines: match the impedance or pay the loss

    RF energy must see a constant characteristic impedance (Z₀) — almost always 50 Ω for single-ended, 100 Ω differential — from source to load. A mismatch reflects power: a 1.5:1 VSWR already wastes ~4% of your signal and can destabilize an amplifier. The geometry sets Z₀, so the stackup is a design input, not an afterthought.

    StructureWhen to useZ₀ driver
    MicrostripTop-layer RF, antennas, easy probingTrace width / height above plane
    Grounded coplanar waveguide (GCPW)>6 GHz, lower dispersion, tight coupling controlTrace width + gap to side ground
    StriplineIsolated inner-layer routing, best shieldingTrace width between two planes

    Practical numbers: on 1.6 mm FR-4, a 50 Ω microstrip is ~2.9 mm wide; drop the dielectric to a 0.2 mm Rogers prepreg and the same 50 Ω line is only ~0.44 mm. Use a 2D field solver — Keysight ADS LineCalc, the Cadence AWR TXLine utility, or the solver inside Siemens HyperLynx / Polar Si9000 — rather than closed-form equations, which lose accuracy near connector launches and bends. Field solvers from Synopsys (via their signal-integrity flow) and Cadence Clarity 3D handle the full launch discontinuity.

    • Avoid 90° corners — they add capacitance and reflect. Use two 45° miters or a smooth radius.
    • Keep lengths short and tapers gradual. A sharp width change is a discontinuity; taper over at least a few trace widths.
    • Design the connector launch. The transition from a coax/SMA to microstrip is where most VSWR is lost; back-drill or counterbore and add ground vias right at the pad.
    Reflection at an impedance step 50 Ω matched line 75 Ω mismatch Z step incident power → ← part reflects at the discontinuity Γ = (75 − 50) / (75 + 50) = 0.2, so 4% of power reflects CourseTron · coursetron.com
    Energy reaching an impedance step is partly reflected (Γ = (Z_L−Z₀)/(Z_L+Z₀)). Watch the pulse bounce back from the 75 Ω section.

    Component placement: shrink every loop

    RF placement is about geography before routing. Order parts along the signal chain so the flow is a straight line — antenna → matching network → filter → LNA/PA → mixer — with no backtracking. Specific rules:

    • Decoupling caps go at the pin, not "nearby." A 100 pF cap 3 mm away with a 2 mm via adds enough inductance to resonate below your band. Place the smallest-value cap closest, with its own ground via.
    • Match networks hug the active device. Series/shunt elements for a PA output must sit within a fraction of a wavelength or the match you simulated won't exist on the board.
    • Isolate hot and quiet domains. Keep the PA output physically far from the LNA input and crystal; use ground pours and via fences as walls.
    • Orient inductors orthogonally to minimize mutual coupling, and keep them off reference planes that spoil their Q.

    Key fact: A typical 0402 cap plus its pads and a single via presents ~1.2 nH. At 2.4 GHz that reactance (~18 Ω) can dominate the intended 1–2 Ω cap impedance — which is why placement, not value, often decides whether decoupling works.

    Place parts along the signal chain Antenna Matching Filter LNA / PA Mixer One straight flow, no backtracking Match network hugs the active device; decoupling cap sits at the pin CourseTron · coursetron.com
    Order components along the signal path: antenna, matching network, filter, LNA/PA, mixer.

    These same loop-area and return-path disciplines underpin digital work too; see our guide to high-speed PCB design guidelines and the companion piece on PCB stackup and impedance control for the layer-planning side. For hands-on, tool-driven practice across both domains, explore the full CourseTron course catalog. Teams needing a production RF board laid out and signed off can also work with the design engineers at Avecas design services.

    Ready to lay out your first working 2.4 GHz board? CourseTron's RF & Microwave PCB Layout track takes you from stackup math to a bench-verified antenna match with real field solvers.

    Frequently asked questions

    Can I do RF layout on standard FR-4?

    Up to roughly 3–6 GHz, yes, if you control the stackup and accept higher loss. Above that, FR-4's loss tangent and εr variation across panels force a move to Rogers or PTFE laminates for repeatable impedance and acceptable insertion loss.

    How many ground vias do I really need around a trace?

    Space stitching vias at about λ/20 in the dielectric so the plane looks continuous to the fields. At 2.4 GHz on FR-4 that is roughly every 3 mm; higher frequencies need tighter spacing.

    Why 50 Ω and not some other impedance?

    50 Ω is a historical compromise between the lowest-loss coax impedance (~77 Ω) and the highest power-handling impedance (~30 Ω). The RF ecosystem — connectors, instruments, amplifier reference designs — standardized on it, so matching to 50 Ω keeps every part compatible.

    Microstrip or grounded coplanar waveguide?

    Use microstrip for simplicity and easy probing below ~6 GHz. Choose GCPW when you need tighter field confinement, lower dispersion, and better isolation at higher frequencies — at the cost of extra side-ground vias.

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