In short: Routing a multi-gigabit bus on a PCB comes down to three disciplines done together — holding the trace to a target differential impedance (typically 85 or 100 Ω), matching the two legs and the lanes tightly in length, and keeping an uninterrupted return path directly beneath every signal so the high-frequency current never has to detour.
When your bus moves at hundreds of Mbps a copper trace behaves like a wire. When it moves at multi-gigabit rates — 5 GT/s PCIe, 10 Gbps SFP+, 6 Gbps SATA, or a DDR4 byte lane toggling at 1.6 GHz — that same trace is a transmission line, and the rules change completely. The rise time, not the clock frequency, sets the demand: a 50 ps edge contains energy past 7 GHz regardless of how often it occurs. At those frequencies reflections, crosstalk and ground bounce turn a schematically-correct net into a link that will not train. This guide walks through the three pillars every physical designer must get right.
1. Controlled Impedance: Why 50 and 100 Ω Keep Appearing
A transmission line has a characteristic impedance Z₀ set by its geometry — trace width, dielectric height to the reference plane, copper thickness, and the dielectric constant (Dk) of the laminate. If the source, line and load impedances all agree, the edge launches, travels and is absorbed with no reflection. Where they disagree, a fraction of the wave bounces back, and the reflection coefficient is Γ = (Z_L − Z₀)/(Z_L + Z₀). A 100 Ω differential pair terminated into 80 Ω reflects about 11% of the edge — enough to close a marginal eye.
Single-ended nets (DDR address/command, legacy buses) target 50 Ω. Differential buses target a differential impedance: USB, PCIe and most SerDes use 85–100 Ω, Ethernet and DDR differential clocks 100 Ω. You do not guess these numbers — you hand your stackup to a 2D field solver. Polar SI9000, the Saturn PCB toolkit, or the solvers inside Cadence Sigrity and Siemens HyperLynx compute width and spacing from the exact prepreg Dk and height your fabricator will use.
⚡ A common FR-4 microstrip of 0.1 mm height (Dk ≈ 4.3) lands near 50 Ω at roughly 0.18 mm trace width. Change the dielectric height and the width must track it — impedance is a ratio, so the stackup and the trace are one design, never two.
2. The Return Path: The Rule Everyone Forgets
Every signal current needs a return. At low frequency it takes the lowest-resistance path home. Above a few megahertz it takes the lowest-inductance path, which is the copper directly under the trace, mirroring it. This is the single most misunderstood idea in high-speed design: the plane under your trace is part of the transmission line, not a passive backdrop.
When a trace crosses a split or gap in its reference plane, the return current cannot follow underneath. It detours around the slot, enlarging the current loop, raising inductance, and radiating. A high-speed net routed over a power-plane split is the classic cause of an EMC failure that no amount of edge-rate tuning will fix. The same happens at a layer change: a signal via that has no adjacent ground (stitching) via forces the return to hunt for the nearest plane connection.
?️ Place a ground stitching via within ~1 mm of every high-speed signal via that changes reference layers. Without it, the return current's detour can add nanohenries of loop inductance and dump broadband noise into your planes.
3. Length Matching: Within the Pair and Across the Bus
Two kinds of skew matter. Intra-pair skew is the length mismatch between the + and − legs of one differential pair; any mismatch converts pure differential signalling into common-mode noise, which radiates and erodes the eye. Inter-pair (or inter-lane) skew is the arrival-time spread across the parallel bits of a bus — the eight data lines of a DDR byte group, or the lanes of a parallel camera interface — which must all land inside the sampling window.
Convert the time budget to a length using the signal's propagation delay. In FR-4 a signal travels at roughly 6 ps/mm (about 165 ps/inch) on an inner stripline. So a 5 ps intra-pair limit is under 1 mm of mismatch. Tools like Cadence Allegro, Siemens Xpedition and Altium enforce these as matched-length and relative-propagation-delay rules, adding accordion/serpentine trombones automatically where a route runs short.
| Bus | Target Z (diff) | Typical intra-pair skew | Inter-pair / lane match |
|---|---|---|---|
| USB 3.x (5–10 Gbps) | 90 Ω | < 5 ps | per-pair, loose |
| PCIe Gen3/4 | 85 Ω | < 5 ps | < 15 ps across lane |
| DDR4 data (DQ/DQS) | 100 Ω (diff clk) | < 2–5 ps | within byte group < ~10 mil |
| Gigabit/10G Ethernet | 100 Ω | < 5 ps | per-pair |
One subtlety: match length by delay, not geometry. A serpentine squeezed too tightly couples to itself and effectively speeds up, so a visually "equal" route can still be electrically short. Keep serpentine spacing at least three trace widths, and place the tuning near the mismatch, not at the far end.
4. Putting It Together: A Routing Checklist
- Lock the stackup first and solve impedance against the fab's real Dk and prepreg heights.
- Route each pair over a single, continuous reference plane; never cross a plane split.
- Reference high-speed signals to ground, not power, wherever possible.
- Stitch ground vias beside every layer-changing signal via.
- Tune intra-pair skew before inter-pair; symmetry in the pair comes first.
- Keep pairs apart (3× dielectric height edge-to-edge) to limit crosstalk, and back-drill long via stubs on 10G+ links.
These topics build directly on the fundamentals in our signal integrity basics primer, and pair naturally with proper PCB stackup design. Teams needing production-grade layout can also lean on professional PCB and silicon design services from Avecas for complex multi-gigabit boards.
Want to simulate eye diagrams and run real return-path experiments? The hands-on CourseTron High-Speed PCB & Signal Integrity course walks you from stackup to sign-off with HyperLynx and Sigrity.
Frequently Asked Questions
Does controlled impedance matter if my traces are short?
It depends on edge rate, not board size. The rule of thumb is that a trace behaves like a transmission line when its length exceeds about one-sixth of the rise-time's wavelength. With a 50 ps edge that is only a few millimetres, so even short multi-gigabit traces need controlled impedance.
Can I route a high-speed signal over a gap in the ground plane?
No. The high-frequency return current cannot follow under the gap, so it detours, inflating loop inductance and radiating. If a plane must be split, keep high-speed nets entirely on one side or bridge the return with a stitching capacitor placed right at the crossing.
How tightly do I really need to length-match a differential pair?
Match the two legs to a few picoseconds of delay — under roughly 1 mm on FR-4. Mismatch turns differential energy into common-mode noise, which hurts both the eye and EMC far more than a small absolute length difference does.
Which EDA tools handle this automatically?
Cadence Allegro/Sigrity, Siemens Xpedition/HyperLynx and Altium Designer all enforce impedance, matched-length and relative-delay constraints, and auto-insert tuning. The physics is still yours to specify; the tool only enforces the rules you set.