Altium Design Rules and Constraints

In short: Altium Designer stores every electrical, routing, plane and manufacturing requirement as a scoped rule, and when several rules of the same type match the same object, the one with the lowest priority number (priority 1) wins, so you build a few broad defaults and layer narrow, higher-priority exceptions on top.

Why a rule system exists at all

A modern board is not drawn so much as constrained. A DDR4 byte lane, a 48 V motor rail and a 0.5 mm pitch BGA breakout all live on the same stackup, yet each needs different spacing, copper width and via behaviour. Altium keeps those requirements in the PCB Rules and Constraints Editor (Design > Rules). The editor drives both the interactive router and the online and batch Design Rule Check (DRC), so the same number that guides your cursor also decides whether the board passes release. It is the same idea as constraint managers in Cadence Allegro or Siemens Xpedition, and understanding it deeply is a common interview topic. If you need the basics first, read our overview of PCB design rules.

Anatomy of a rule: type, scope and value

Every rule has three parts. The type (Clearance, Width, Plane Clearance and so on) says what is checked. The scope is a query that says which objects it applies to, such as All, InNet('GND'), InNetClass('HighVoltage') or OnLayer('Top Layer'). The constraint holds the numbers. Binary rules such as Clearance have two scopes, a first object and a second object, because spacing is a relationship between two things. Unary rules such as Width have one.

Key fact: Rules are grouped by category: Electrical, Routing, SMT, Mask, Plane, Testpoint, Manufacturing, High Speed, Placement and Signal Integrity. Priority is only compared between rules of the same type.

Clearance rules and the 3W intuition

The Electrical > Clearance rule sets minimum copper-to-copper gap. A sensible default for a 1 oz standard fabrication is 6 to 8 mil (0.15 to 0.2 mm), matching what most low-cost fabs hold reliably. Altium evaluates the gap between every pair of objects, track to pad, via to polygon, and so on, so you can tighten a rule for one pair without touching the others. For safety isolation, creepage and clearance tables such as IPC-2221 suggest roughly 0.6 mm for 100 to 150 V between uncoated external conductors, and far more for mains. That belongs in a separate rule whose scope is InNetClass('Mains') against All.

The "first object matches" and "second object matches" pair is the part candidates fumble. A rule with First = InNet('HV') and Second = All applies when either object belongs to HV, so a single entry covers HV against everything. For the underlying manufacturing limits behind these numbers, see PCB design for manufacturing.

Routing width, via style and layers

Routing > Width has three numbers: minimum, preferred and maximum. The router starts at preferred, DRC flags anything outside min/max, and you can switch width on the fly with Shift+W. A typical stack of rules looks like this: All = 6 / 8 / 20 mil, InNetClass('Power') = 20 / 30 / 100 mil, and InDifferentialPair('USB') managed by a Differential Pairs Routing rule so that the gap and width hold 90 Ω differential impedance. Width is a current question as well: on 1 oz external copper, IPC-2221 gives about 1 A for roughly 10 mil at a 10 °C rise, and about 3 A for around 50 mil, so power rules are not decoration.

Routing Via Style defines hole size and pad diameter ranges. Preferred 0.3 mm / 0.6 mm vias suit general nets, while a BGA fanout class might use 0.2 mm / 0.45 mm microvias, as covered in via types in PCB and HDI PCB design. Pair that with Manufacturing > Hole Size, Minimum Annular Ring (commonly 4 to 5 mil) and Hole to Hole Clearance so the fab limits are checked even if someone edits a via by hand.

Routing Layers is the one people forget. Set the rule so that InNetClass('Clocks') may route only on the layers adjacent to a plane, and the autorouter and interactive router will refuse the others. This is how you enforce reference-plane continuity from the stackup rather than relying on memory.

Key fact: Routing Priority (a separate rule type) only influences the autorouter's net order. It is unrelated to rule priority, a naming collision that confuses many candidates.

Plane rules: clearance and connection

Plane rules matter on internal layers. Power Plane Clearance (Plane category) removes copper around vias and pads that belong to other nets, commonly 10 to 20 mil. Power Plane Connect Style decides what happens for same-net pins: relief connect with four 10 mil spokes is the thermally friendly default, while direct connect gives the lowest inductance and is preferred for decoupling-capacitor vias and high-current pins. Polygon Connect Style does the same for poured polygons on signal layers. A classic mistake is relief-connecting a 5 A regulator output pad, which throttles current through four narrow spokes and overheats during reflow rework. Use a scoped rule, InNet('VOUT'), with direct connect and higher priority.

How priorities actually resolve conflicts

Within one rule type, Altium sorts rules by priority and uses the first one whose scope matches the object (or object pair). Priority 1 is the highest. The Edit Rule Priorities dialog lets you drag the order, and there is no "most restrictive wins" logic, which surprises engineers. If a broad Clearance of 10 mil sits above a specific 6 mil rule for a BGA region, the BGA gets 10 mil, DRC fails, and the board will not route. The working method: put the narrowest, most special scopes first, general rules next, and an All default last. A rule with scope All at priority 1 silently masks every rule below it.

A practical rule-building workflow

• Define net classes first (Design > Classes) so that scopes read cleanly: Power, HV, Clocks, DDR_Data.
• Import the fab's capability sheet and set default Clearance, Width, Hole Size and Annular Ring from it.
• Add narrow exceptions, then reorder priorities so exceptions sit above defaults.
• Run batch DRC early and often (Tools > Design Rule Check), and use the Rules and Violations panel to see which rule fired.
• Export the rules (.RUL) as a reusable template for the next project, so lessons survive between boards.

This fits into the broader PCB design flow between schematic capture and release, and it mirrors the standards you meet in PCB design standards. Our sister training brand ChipXpert covers hardware career paths if you are planning a move into board or silicon design.

Key fact: If a clearance seems ignored, check priority order first, then the scope query syntax, and only then the rule value.

Want to practise writing scoped rules on a real multilayer board? Explore the hands-on PCB tracks in our CourseTron courses.

FAQ

Does Altium apply the most restrictive rule automatically?

No. It applies the first matching rule in priority order. If a looser rule outranks a tighter one, the looser value is used.

What is the difference between rule priority and routing priority?

Rule priority orders rules of the same type for conflict resolution. Routing Priority is itself a rule type that sets which nets the autorouter handles first.

When should I use direct connect instead of relief connect?

Use direct connect for high-current pins and decoupling vias where low inductance matters, and relief connect for ordinary pads that must be hand-soldered or reworked.

Can one clearance rule cover all high-voltage nets?

Yes. Put the nets in a class and use First = InNetClass('HV'), Second = All at a high priority.