In short: A through-silicon via (TSV) is a copper-filled vertical shaft etched straight through a thinned silicon wafer, letting stacked dies and HBM memory talk through microns of interconnect instead of millimetres of wire-bond or board trace.
For decades, the only way to get a signal off a chip was sideways: out to a pad on the die edge, down a wire bond or bump, across a package, and onto the board. Three-dimensional integration throws that geometry out. Instead of routing around the silicon, a through-silicon via punches a conductive path through it, so a die sitting on top of another die can reach the one below with a connection that is tens of microns long rather than several millimetres. That single change is what makes modern logic-on-logic stacks and High Bandwidth Memory (HBM) physically possible.
Why go vertical at all?
The motivation is brutally simple arithmetic. Interconnect delay scales with the square of wire length, and capacitance scales with length too. A traditional DDR interface might drive a signal 30–40 mm across a motherboard; an HBM stack sitting on the same interposer as the GPU drives it a few millimetres, and inside the stack a TSV carries it perhaps 50 µm. Shorter means lower RC delay, lower energy per bit, and the freedom to run a very wide, slow bus instead of a narrow, frantic one.
Numbers that matter: HBM3 exposes a 1024-bit-wide interface per stack running at a modest ~3.2 GT/s per pin, delivering ~820 GB/s. A single HBM stack contains several thousand TSVs. Energy per bit drops to roughly 1 pJ/bit versus 15–20 pJ/bit for conventional off-package DRAM.
That is the whole trick: width beats frequency. You cannot route a thousand-bit bus off a die edge, but you can drop a thousand vias straight down through it.
How a TSV is actually built
The dominant recipe is the "via-middle" flow, built after the transistors (front-end-of-line) but before the upper metal layers. The sequence looks like this:
- Etch: A deep reactive-ion etch (the Bosch process) alternates etch and passivation cycles to drill a high-aspect-ratio hole — typically 5–10 µm in diameter and 50 µm deep, giving aspect ratios of 10:1 or more.
- Liner + barrier: A thin oxide liner insulates the via from the silicon; a barrier (TaN/Ta) stops copper from poisoning the transistors.
- Seed and fill: A copper seed is sputtered, then the via is bottom-up electroplated with Cu. Void-free filling of a 10:1 hole is the hard part.
- CMP: Chemical-mechanical polish removes the copper overburden.
- Thin and reveal: The wafer is ground from the back down to ~50 µm so the buried via tips are "revealed," then microbumps are formed for stacking.
There are also "via-first" (before transistors) and "via-last" (after metal, from the back) variants. Via-middle dominates for logic because it tolerates the thermal budget of later processing without disturbing devices.
The keep-out zone and thermo-mechanical stress
Copper has a coefficient of thermal expansion roughly 5× that of silicon. Every thermal cycle, the Cu via pushes and pulls on the surrounding lattice, creating a stress field that shifts carrier mobility in nearby transistors. Designers must therefore define a keep-out zone (KOZ) — typically a few microns of silicon around each via where no sensitive device may be placed.
Design rule reality: TSV diameter, pitch, KOZ, and liner thickness are all captured in the foundry's 3D design kit. Tools like Cadence Integrity 3D-IC, Synopsys 3DIC Compiler, and Ansys/Siemens for thermal and stress sign-off let you place, route, and verify across stacked dies as one system rather than as isolated chips.
Electrical and thermal challenges
A TSV is not a free wire. Key non-idealities an interview will probe:
- Capacitance: The MOS capacitor formed by the Cu conductor, oxide liner, and silicon substrate couples signals into the bulk — a few tens of fF per via, worse at low substrate bias.
- Resistance and EM: Small cross-sections raise resistance and electromigration risk at high current.
- Thermal bottleneck: Stacking logic on logic traps heat. The top die cannot dump heat through the dies below it easily, so dummy "thermal TSVs" are often added purely to conduct heat, not signal.
- Test and yield: Known-good-die testing before stacking is essential — one bad die in a 12-high stack scraps the whole stack.
| Interconnect | Typical length | Energy/bit | Density |
|---|---|---|---|
| Board trace (DDR) | 20–40 mm | ~15–20 pJ | Low |
| Interposer (2.5D) | 1–5 mm | ~1–2 pJ | High |
| TSV (3D) | ~50 µm | ~0.1–1 pJ | Very high |
If you want the broader packaging context — how TSVs sit inside interposers, bridges, and chiplet stacks — see our companion piece on 2.5D and 3D IC packaging, and for the etch and deposition fundamentals behind the via itself, our notes on deep reactive-ion etching. Teams building real stacks for tape-out often lean on specialised physical-design and sign-off support such as that offered by Avecas VLSI design services.
Where TSVs show up today
The flagship application is HBM — every HBM2/2E/3 stack is a tower of DRAM dies bonded by thousands of TSVs over a base logic die, feeding GPUs and AI accelerators. Beyond memory, CMOS image sensors stack a pixel array over a logic die using TSVs, and FPGAs like AMD/Xilinx's early 2.5D parts used TSV interposers to stitch slices together. The industry is now moving toward hybrid Cu-Cu bonding that shrinks pitch below what microbumps allow, pushing die-to-die connections into the sub-micron regime.
Want to build these flows hands-on? CourseTron's Nano Fabrication track walks through TSV process integration, 3D-IC design kits, and thermal sign-off with real EDA tools. Explore the CourseTron courses →
FAQ
What is the difference between a TSV and a microbump?
A TSV is the vertical conductor running through the silicon of a single die. A microbump is the solder connection between two stacked dies. A signal travels down a TSV, across a microbump, then down the next die's TSV.
Why is copper used to fill TSVs?
Copper has the low resistivity needed for thousands of parallel connections and plates well bottom-up. Its main drawback is a large thermal-expansion mismatch with silicon, which is why keep-out zones and barrier liners are mandatory.
What limits how many dies you can stack?
Heat and yield. Dies deep in the stack cannot shed heat easily, and because the whole stack is scrapped if any die fails, cumulative yield falls with height. Known-good-die testing and thermal TSVs mitigate both.
Is a TSV the same as a 2.5D interposer?
No. A 2.5D interposer places dies side-by-side on a shared silicon slab (which itself uses TSVs to reach the package). True 3D stacking places dies directly on top of each other, connected by TSVs through each die.