In short: Photolithography is the step that prints a circuit pattern onto a silicon wafer by exposing a light-sensitive resist through a mask and developing away the soluble regions. That patterned resist then acts as a stencil for etching or implantation, and the shortest feature it can reliably print is set by the exposure wavelength, the lens numerical aperture, and the process k1 factor.
Photolithography (literally "light-stone-writing") is the patterning engine of semiconductor manufacturing. Every transistor, contact, and metal wire on a modern chip begins as a shape on a photomask that is optically transferred onto a wafer. A single leading-edge chip may pass through the photolithography module 60 to 80 times, once for each patterned layer, which is why the exposure tool (the "scanner") is the most expensive piece of equipment in the fab.
The core idea is simple: coat the wafer with a polymer whose solubility changes where light strikes it, project the mask image onto that polymer, then dissolve the parts you no longer want. What remains is a precise relief pattern that protects the wafer underneath during the next processing step.
A production lithography cell runs a tightly choreographed sequence on a "track" tool clustered around the scanner. The main stages are below.
A few millilitres of photoresist are dispensed onto the wafer centre and spun at 1,000–4,000 rpm. Centrifugal force spreads the liquid into a remarkably uniform film, typically 30–500 nm thick, whose thickness scales roughly with the inverse square root of spin speed. A soft bake (around 90–110 °C) then drives off casting solvent and stabilises the film. Modern resists are chemically amplified: a photoacid generator embedded in the polymer releases acid on exposure, and a short post-exposure bake lets that acid catalytically change many polymer sites per photon, boosting sensitivity.
The coated wafer moves into the scanner. Light from the source passes through the photomask (reticle), and a reduction lens, usually 4×, projects a demagnified image of the mask onto a small field of the wafer. A step-and-scan tool exposes one field, steps to the next, and repeats across the whole wafer. For positive resist, the exposed regions become soluble; for negative resist, exposure cross-links the polymer so the unexposed regions dissolve instead. Dose and focus are controlled to the single-nanometre and single-millijoule level.
After the post-exposure bake, the wafer is flooded with a developer, typically 0.26 N tetramethylammonium hydroxide (TMAH). The developer dissolves the soluble resist regions and leaves a three-dimensional relief that mirrors the mask. Critical-dimension (CD) metrology and overlay checks follow: the printed linewidth and the alignment to the layer beneath are measured, and out-of-spec lots are stripped and reworked before any permanent step occurs.
The developed resist is only a temporary stencil. In pattern transfer the wafer goes to etch, where plasma or wet chemistry removes the exposed film while the resist protects the covered areas, or to ion implantation, where the resist blocks dopants from masked regions. Once transfer is complete the resist has done its job and is stripped with oxygen plasma (ashing) or solvents, leaving the patterned layer behind. The loop then repeats for the next layer.
Resolution is ultimately an optics problem. Because the lens captures only a finite cone of diffracted light, fine features blur. The animation below shows the exposure light sweeping across the mask-to-wafer projection that defines each printed line.
With i-line and early DUV tools, shrinking λ was straightforward. But 193 nm immersion (water between lens and wafer, raising effective NA to about 1.35) stalled near the 38 nm half-pitch, and no practical lithographic wavelength existed between 193 nm and EUV's 13.5 nm. The industry responded with a toolbox of resolution enhancement techniques:
Extreme ultraviolet lithography finally reduced the wavelength to 13.5 nm, letting a single EUV exposure replace multi-patterning stacks at the most aggressive layers, though it brought its own challenges in source power, reflective optics, and stochastic defects.
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Explore CourseTron Courses →In positive resist the exposed regions become soluble and wash away, so the developed pattern matches the clear areas of the mask. In negative resist exposure cross-links the polymer, so the unexposed regions dissolve and the pattern is inverted. Most advanced logic uses positive-tone chemically amplified resists.
Masks are written at roughly 4× the final feature size because it is far easier to fabricate and inspect a larger reticle. The projection lens then demagnifies the image by 4× onto the wafer, relaxing mask tolerances and reducing the impact of mask defects on the printed chip.
The Rayleigh equation CD = k1λ/NA governs it. A shorter exposure wavelength, a higher numerical aperture, and a smaller process k1 (via illumination tricks and multiple patterning) all reduce the minimum printable half-pitch, with a hard single-exposure floor near k1 = 0.25.
A leading-edge logic chip can require 60 to 80 masked lithography layers, since every transistor, contact, via, and metal interconnect level is patterned separately and must align to the layers beneath it within a few nanometres of overlay error.
Related: EUV lithography · Glossary · all courses.