In short: Optical proximity correction (OPC) deliberately distorts the mask shapes so that, after light diffracts through a sub-wavelength lithography system, the pattern that actually prints on the wafer matches the designer's intended layout.
By the time a feature is a fraction of the exposure wavelength, the photomask is no longer a faithful stencil. A clean rectangle on the mask prints as a rounded, shrunken blob on silicon, line ends pull back, and a wide line next to a narrow line prints a different width than the same narrow line in isolation. OPC is the computational step in the mask data-prep flow that pre-compensates for all of this. It is one of the most compute-intensive stages in the entire semiconductor flow and a core topic for anyone working in lithography, DFM, or mask engineering.
Why a mask stops being a simple stencil
Projection lithography is a diffraction-limited imaging system. The smallest half-pitch it can resolve is governed by the Rayleigh criterion, CD = k1 · λ / NA. For a long time the industry printed features far smaller than the wavelength: 193 nm ArF immersion scanners (λ = 193 nm, NA up to 1.35) were pushed to print 40 nm and tighter features, pushing k1 toward its hard floor near 0.25. EUV at 13.5 nm with NA 0.33 (0.55 for High-NA) relaxes the ratio but does not eliminate the problem.
When the feature size approaches λ, the higher diffraction orders that carry fine detail fall outside the lens aperture and never reach the wafer. The image low-pass filters: corners round off, small jogs vanish, and the printed edge placement drifts. Two distortions dominate practical OPC: optical proximity effects (a feature's printed width depends on its neighbors' spacing) and line-end shortening (the tip of a line pulls back from its drawn endpoint).
Key fact: At the 193 nm immersion node printing 40 nm lines, features are roughly one-fifth of the exposure wavelength. Without RET and OPC, those layers would be physically unprintable with acceptable yield.
Rule-based vs. model-based OPC
Early OPC (down to ~250–130 nm) was rule-based: a lookup table said "if a line is isolated, bias its width +8 nm; if the space is <180 nm, add a hammerhead of X on the line end." It was fast but brittle, and it broke down once the number of interacting neighbors exploded.
Modern nodes use model-based OPC (MB-OPC). The drawn polygon edges are chopped into short fragments (often 20–60 nm each). A calibrated optical + resist model — built from SEM measurements of hundreds of test structures — predicts where each fragment will print. An optimizer then nudges each fragment in or out and re-simulates, iterating until the simulated contour sits within an edge-placement-error (EPE) budget, often a few nanometers, of the target. Production engines include Synopsys Proteus, Siemens EDA (Mentor) Calibre OPC, and Cadence's mask-synthesis tools. A full-chip MB-OPC run on a leading logic layer can consume tens of thousands of CPU-core-hours.
SRAFs: printing nothing on purpose
Sub-resolution assist features (SRAFs, also called scattering bars) are thin lines placed next to a main feature but sized deliberately below the resolution limit so they never print. Their job is to make an isolated line "see" the same diffraction environment as a dense line, flattening the proximity curve and widening the process window (the overlap of depth-of-focus and exposure latitude). A classic example: a lone gate line gets two scattering bars flanking it, so its through-focus behavior matches gates sitting in a dense array. Inverse lithography technology (ILT) takes this further, solving for freeform, often curvilinear mask shapes directly from the target image rather than editing rectangles — at much higher compute cost.
Key fact: SRAFs are a resolution enhancement technique (RET), alongside off-axis illumination and phase-shift masks. OPC, SRAF insertion, and these RETs are applied together — OPC alone cannot rescue a layer that lacks illumination optimization.
The correction flow, step by step
A typical model-based correction on a critical layer runs like this:
- Target extraction — read the layer from GDSII/OASIS and define the desired on-wafer contour.
- SRAF / RET insertion — place assist features and apply the chosen illumination/phase scheme.
- Fragmentation — cut main-feature edges into movable segments.
- Simulate & measure EPE — compute the aerial + resist image, measure error at each fragment.
- Move & iterate — displace fragments, re-simulate, typically 5–15 passes.
- Verification (LRC/ORC) — a litho-rule / optical-rule check flags pinching, bridging, and insufficient process window before the data goes to the mask shop.
| Issue | Symptom on wafer | OPC/RET remedy |
|---|---|---|
| Corner rounding | Rounded contacts, lost area | Serifs on outer / inner corners |
| Line-end shortening | Tip pullback, open contact | Hammerheads on line ends |
| Iso-dense bias | Isolated line prints wider/narrower | SRAFs + off-axis illumination |
| Poor depth of focus | CD swings through focus | Phase-shift mask, ILT |
OPC is also governed by DFM constraints handed down from design. For how the upstream physics drives all of this — and why EUV changes the correction budget — see our companion piece on EUV lithography, and the deeper treatment in photomask fabrication. Teams building full mask-synthesis flows often pair this with hands-on tool training from ChipXpert's VLSI programs.
Want to run a real model-based OPC and ILT flow on sample layers, and read an aerial image yourself? Our CourseTron Nano Fab track walks through diffraction, RET, and mask data-prep end to end.
Frequently asked questions
Is OPC still needed with EUV?
Yes. EUV's shorter 13.5 nm wavelength relaxes k1 but still prints sub-wavelength features, and it adds new effects such as stochastic edge roughness and mask 3D (shadowing) that OPC and RET must model. The correction is smaller than at 193 nm but far from zero.
What is edge placement error (EPE)?
EPE is the distance between where a corrected edge actually prints (the simulated or measured contour) and where it was targeted. It is the primary cost function MB-OPC minimizes, typically down to a budget of a few nanometers per fragment.
Do SRAFs ever print by mistake?
They can if sized too aggressively or under focus/dose excursions — that is exactly what the ORC/LRC verification step catches. A printing SRAF is a yield defect, so the engine keeps assist features safely below the resolution limit.
Rule-based or model-based — which do fabs use today?
Leading logic and DRAM layers are model-based (and increasingly ILT with machine-learning acceleration). Rule-based OPC survives on mature, relaxed-pitch layers where speed matters more than precision.