In short: IC packaging takes a fragile silicon die, connects its micron-scale I/O pads to a sturdy substrate or leadframe using wire bonds or flip-chip bumps, encapsulates it against mechanical and environmental damage, and presents board-friendly leads or balls — trading electrical performance, thermal budget, and cost across families from the humble DIP to the 2.5D/3D interposer stacks that power today's AI accelerators.
Ask any VLSI engineer what "finishes" a chip and they will say tape-out. Ask a product engineer and they will tell you the real work starts there. A bare die straight off the wafer is a piece of silicon roughly 0.1–0.8 mm thick with bond pads 40–80 µm wide — far too delicate to solder onto a PCB and far too small for any human-scale assembly line. Packaging is the discipline of turning that die into a reliable, handleable, testable component. It is where the back-end-of-line meets the real world, and it increasingly decides whether a system is competitive.
Why packaging exists: four jobs in one
A package does four things at once. It provides mechanical protection — guarding the die against handling, vibration, and moisture. It supplies electrical interconnect — fanning out hundreds or thousands of tiny die pads to a pitch a board can accept (typically 0.4–1.0 mm). It manages heat — moving power dissipation off the junction before it cooks the transistors. And it enables test and handling, giving automated equipment something to grip, socket, and burn in. Every package family is a different compromise between these four jobs plus cost.
Key fact: Pad pitch on a modern die can be under 40 µm, while a board via is around 200–300 µm. The package's core job is this ~10× geometric fan-out — do it badly and you pay in signal integrity, yield, and dollars.
From wafer to connected die
The assembly flow is remarkably consistent across families. After wafer probe sorts good die from bad, the wafer is thinned by backgrinding (often to 100–300 µm so stacks stay flat), then diced on a saw or laser into individual dies. Each good die is picked and attached to a substrate or leadframe with a die-attach epoxy or solder. Then comes the electrical connection — the step that most sharply divides the families — followed by encapsulation (molding or a lid), ball or lead formation, singulation, and final test.
Wiring the die: bond vs. bump
There are two dominant ways to connect die pads to the package.
Wire bonding is the workhorse. A fine gold, copper, or silver wire (15–50 µm diameter) is welded from a peripheral die pad to a substrate finger using ultrasonic energy and heat. It is cheap, mature, and forgiving, which is why the overwhelming majority of units shipped worldwide are still wire-bonded. Its limits are inductance (each wire adds ~1 nH, which hurts at GHz speeds) and the fact that pads must live on the die edge, capping I/O count.
Flip-chip turns the die upside down and connects via an area array of solder bumps or copper pillars, often on a 100–150 µm pitch across the whole die face. This slashes interconnect inductance, allows thousands of I/O, and improves thermal paths, but it costs more and demands tight control of underfill and warpage. We cover the trade-offs in depth in our companion piece on wire bonding vs. flip-chip.
Encapsulation: sealing the deal
Once connected, the die must be protected. Low-cost plastic packages are overmolded with an epoxy molding compound in a transfer-mold press — fast and cheap but limited in thermal and hermetic performance. High-reliability parts (aerospace, some automotive, RF) use ceramic or metal-lidded cavity packages that can be hermetically sealed and tolerate wider temperature swings. For flip-chip, a capillary underfill is flowed between die and substrate to match thermal expansion and keep the bumps from fatiguing over thousands of power cycles.
The main package families
Packages have evolved to pack more I/O into less area with better electrical behavior. A rough progression:
| Family | Interconnect | Typical I/O | Where it shines |
|---|---|---|---|
| DIP / through-hole | Leads in two rows | 8–64 | Legacy, hobbyist, high-voltage |
| QFP / QFN | Peripheral leads / pads | 32–256 | MCUs, mixed-signal, power |
| BGA | Solder-ball area array | 256–2,000+ | SoCs, FPGAs, processors |
| Flip-chip BGA (FCBGA) | Bumps + balls | 1,000–10,000+ | CPUs, GPUs, high-speed SerDes |
| WLCSP | Balls directly on die | 4–200 | Phones, sensors, space-limited |
| 2.5D / 3D (interposer, HBM) | µbumps + TSVs | 10,000s | AI/HPC accelerators |
Key fact: A chip-scale package (WLCSP) is barely larger than the die itself — the "fan-out" happens in redistribution layers built on the wafer, so a 2 mm sensor can ship in a 2.1 mm ball-grid footprint.
The frontier is advanced / heterogeneous packaging: splitting a big design into smaller chiplets and reconnecting them on a silicon interposer (2.5D, as in TSMC CoWoS) or stacking them vertically through Through-Silicon Vias (3D). High-Bandwidth Memory (HBM) stacks 8–12 DRAM dies and bonds them beside a GPU, delivering terabytes per second of bandwidth that a wire-bonded board could never match. This is why "the package" is now a first-class design concern, not an afterthought — and why design-services teams such as Avecas treat package co-design alongside RTL and physical design.
Animated view: a signal crossing the interconnect
What packaging means for the designer
Package choice reaches back into the flow. I/O planning, power-delivery network design, and electromigration checks in tools like Synopsys IC Compiler II or Cadence Innovus must respect the bump map. Signal- and power-integrity sign-off uses chip-package-system solvers (Cadence Sigrity, Ansys RedHawk/HFSS), and mechanical stress and warpage are modeled with Siemens Simcenter and finite-element analysis. A beautiful die on a poorly co-designed package will fail power-cycling or lose its highest-speed lanes. Learning to read a package the way you read a netlist is now part of the job — explore it hands-on in our CourseTron courses.
If you want the historical and reliability context behind thermal cycling and solder-joint fatigue, our note on thermal management in IC packages is a good next stop.
Go deeper: CourseTron's Advanced IC Packaging & Assembly track walks you from wire-bond recipes to 2.5D interposer floorplanning with real datasheets and tool labs. Pair it with hands-on fab training from ChipXpert to build an interview-ready portfolio.
Frequently asked questions
Is wire bonding obsolete?
No. By unit volume it still dominates — most microcontrollers, power devices, sensors, and memory ship wire-bonded because it is cheap and robust. Flip-chip and advanced packaging win where I/O count, speed, or thermal density demand it, not everywhere.
What is the difference between a BGA and a flip-chip BGA?
Both present solder balls to the board. In a plain BGA the die is usually wire-bonded inside; in a flip-chip BGA the die itself is bumped face-down onto the substrate, giving much lower inductance and far higher I/O for high-speed parts like CPUs and GPUs.
Why is HBM placed beside the processor instead of on the board?
Bandwidth. Routing thousands of wide-bus signals over a short silicon interposer keeps them fast, low-power, and dense — distances and losses that an ordinary PCB could not support at the same bandwidth.
What is underfill and why does it matter?
Underfill is an epoxy flowed between a flip-chip die and its substrate. It couples the two mechanically so that differences in thermal expansion are shared across the whole area rather than concentrated on individual solder bumps, dramatically improving fatigue life under power cycling.